ch14.8.htm
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<TITLE> 14.8 A Simple Test Example</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
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14.8 <A NAME="36101">
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A Simple Test Example</H1>
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As an example, we will describe automatic test generation using boundary scan together with internal scan. We shall use the function Z = A'B + BC for the core logic and register the three inputs using three flip-flops. We shall test the resulting sequential logic using a scan chain. The simple logic will allow us to see how the test vectors are generated. </P>
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14.8.1 Test-Logic Insertion</H2>
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<A HREF="CH14.8.htm#12145" CLASS="XRef">
Figure 14.31</A>
shows a structural Verilog model of the logic core. The three flip-flops (cell name <SPAN CLASS="BodyComputer">
dfctnb</SPAN>
) implement the input register. The combinational logic implements the function, <SPAN CLASS="BodyComputer">
outp = a_r[0]'.a_r[1] + a_r[1].a_r[2</SPAN>
]. This is the same function as <A HREF="CH14.3.htm#16029" CLASS="XRef">
Figure 14.14</A>
and <A HREF="CH14.4.htm#42019" CLASS="XRef">
Figure 14.16</A>
.</P>
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<B CLASS="Keyword">
module</B>
core_p (outp, reset, a, clk);</P>
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<B CLASS="Keyword">
output</B>
outp; <B CLASS="Keyword">
input</B>
reset, clk; <B CLASS="Keyword">
input</B>
[2:0] a; <B CLASS="Keyword">
wire</B>
[2:0] a_r; </P>
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dfctnb a_r_ff_b0 (.D(a[0]), .CP(clk), .CDN(reset), .Q(a_r[0]), .QN(\a_r_ff_b0.QN ));</P>
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dfctnb a_r_ff_b1 (.D(a[1]), .CP(clk), .CDN(reset), .Q(a_r[1]), .QN(\a_r_ff_b1.QN ));</P>
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dfctnb a_r_ff_b2 (.D(a[2]), .CP(clk), .CDN(reset), .Q(a_r[2]), .QN(\a_r_ff_b2.QN ));</P>
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in01d0 u2 (.I(a_r[0]), .ZN(u2_ZN));</P>
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nd02d0 u3 (.A1(u2_ZN), .A2(a_r[1]), .ZN(u3_ZN));</P>
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nd02d0 u4 (.A1(a_r[1]), .A2(a_r[2]), .ZN(u4_ZN));</P>
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nd02d0 u5 (.A1(u3_ZN), .A2(u4_ZN), .ZN(outp));</P>
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<B CLASS="Keyword">
endmodule</B>
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FIGURE 14.31 <A NAME="12145">
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Core of the Threegates ASIC.</P>
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<A HREF="CH14.8.htm#27423" CLASS="XRef">
Table 14.15</A>
shows the structural Verilog for the top-level logic of the Threegates ASIC including the I/O pads. There are nine pad cells. Three instances <SPAN CLASS="BodyComputer">
(up1_b0</SPAN>
, <SPAN CLASS="BodyComputer">
up1_b1</SPAN>
, and <SPAN CLASS="BodyComputer">
up1_b2</SPAN>
) are the data-input pads, and one instance, <SPAN CLASS="BodyComputer">
up2_1</SPAN>
, is the output pad. These were vectorized pads (even for the output that had a range of 1), so the synthesizer has added suffixes (<SPAN CLASS="BodyComputer">
'_1'</SPAN>
and so on) to the pad instance names. Two pads are for power, one each for ground and the positive supply, instances <SPAN CLASS="BodyComputer">
up11</SPAN>
and <SPAN CLASS="BodyComputer">
up12</SPAN>
. One pad, instance <SPAN CLASS="BodyComputer">
up3_1</SPAN>
, is for the reset signal. There are two pad cells for the clock. Instance <SPAN CLASS="BodyComputer">
up4_1</SPAN>
is the clock input pad attached to the package pin and instance <SPAN CLASS="BodyComputer">
up6</SPAN>
is the clock input buffer. </P>
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The next step is to insert the boundary-scan logic and the internal-scan logic. Some synthesis tools can create test logic as they synthesize, but for most tools we need to perform <SPAN CLASS="Definition">
test-logic insertion</SPAN>
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as a separate step. Normally we complete a parameter sheet specifying the type of test logic (boundary scan with internal scan in this case), as well as the ordering of the scan chain. In our example, we shall include all of the sequential cells in the boundary-scan register and order the boundary-scan cells using the pad numbers (in the original behavioral input). <A HREF="CH14.8.htm#18055" CLASS="XRef">
Figure 14.32</A>
shows the modified core logic. The test software has changed all the flip-flops (cell names <SPAN CLASS="BodyComputer">
dfctnb</SPAN>
) to scan flip-flops (with the same instance names, but the cell names are changed to <SPAN CLASS="BodyComputer">
mfctnb</SPAN>
). The test software also adds a noninverting buffer to drive the scan-select signal to all the scan flip-flops. </P>
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The test software also adds logic to the top level. We do not need a detailed understanding of the automatically generated logic, but later in the design flow we will need to understand what has been done. <A HREF="CH14.8.htm#24939" CLASS="XRef">
Figure 14.33</A>
shows a high-level view of the Threegates ASIC before and after test-logic insertion. </P>
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TABLE 14.15 <A NAME="27423">
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The top level of the Threegates ASIC before test-logic insertion.</P>
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<B CLASS="Keyword">
module</B>
asic_p (pad_outp, pad_a, pad_reset, pad_clk);</P>
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<B CLASS="Keyword">
output</B>
[0:0] pad_outp; <B CLASS="Keyword">
input</B>
[2:0] pad_a; <B CLASS="Keyword">
input</B>
[0:0] pad_reset, pad_clk;</P>
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<B CLASS="Keyword">
wire</B>
[0:0] reset_sv, clk_sv, outp_sv; <B CLASS="Keyword">
wire</B>
[2:0] a_sv; <B CLASS="Keyword">
supply1</B>
VDD; <B CLASS="Keyword">
supply0</B>
VSS;</P>
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core_p uc1 (.outp(outp_sv[0]), .reset(reset_sv[0]), .a(a_sv[2:0]), .clk(clk_bit));</P>
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pc3o07 up2_1 (.PAD(pad_outp[0]), .I(outp_sv[0]));</P>
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pc3c01 up6 (.CCLK(clk_sv[0]), .CP(clk_bit));</P>
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pc3d01r up3_1 (.PAD(pad_reset[0]), .CIN(reset_sv[0]));</P>
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pc3d01r up4_1 (.PAD(pad_clk[0]), .CIN(clk_sv[0]));</P>
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pc3d01r up1_b0 (.PAD(pad_a[0]), .CIN(a_sv[0]));</P>
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pc3d01r up1_b1 (.PAD(pad_a[1]), .CIN(a_sv[1]));</P>
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pc3d01r up1_b2 (.PAD(pad_a[2]), .CIN(a_sv[2]));</P>
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pv0f up11 (.VSS(VSS)); </P>
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pvdf up12 (.VDD(VDD));</P>
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<B CLASS="Keyword">
endmodule</B>
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