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14.12 <A NAME="35863">
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Bibliography</H1>
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Books by Feugate and McIntyre [<A NAME="[Feugate and McIntyre, 1988]">
</A>
1988], Cheng and Agrawal [<A NAME="[Cheng and Agrawal, 1989]">
</A>
1989], and Fritzemeier, Nagle, and Hawkins [<A NAME="[Fritzemeier, Nagle, and Hawkins, 1989]">
</A>
1989] contain explanations of basic testing terms and techniques. The book by Abramovici, Breuer, and Friedman [<A NAME="[Abramovici, Breuer, and Friedman, 1990]">
</A>
1990] is an advanced undergraduate and graduate-level review of test techniques. Needham’s [<A NAME="[Needham, 1991]">
</A>
1991] book reviews wafer and package testing. The text by Russell and Sayers [<A NAME="[Russell and Sayers, 1989]">
</A>
1989] is an undergraduate-level text with explanations of test algorithms. Turino’s [<A NAME="[Turino, 1990]">
</A>
1990] book covers a wide range of testing topics. </P>
<P CLASS="Body">
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There are a number of books with collections of research papers on test, including works by Eichelberger, Lindblom, Waicukauski, and Williams [<A NAME="[Eichelberger, Lindblom, Waicukauski, and Williams, 1991]">
</A>
1991]; Lombardi and Sami [<A NAME="[Lombardi and Sami, 1987]">
</A>
1987]; Williams [<A NAME="[Williams, 1986]">
</A>
1986]; and Zobrist [<A NAME="[Zobrist, 1993]">
</A>
1993]. Tsui’s book contains a review of scan test and a large bibliography [<A NAME="[Tsui, 1987]">
</A>
1987]. The book by Ghosh, Devadas, and Newton [<A NAME="[Ghosh, Devadas, and Newton, 1992]">
</A>
1992] describes test-generation algorithms for state machines at a level intended for CAD researchers. Bardell, McAnney, and Savir [<A NAME="[Bardell, McAnney, and Savir, 1987]">
</A>
1987] focus on pseudorandom BIST. A book by Yarmolik [<A NAME="[Yarmolik, 1990]">
</A>
1990] covers BIST and signature analysis; a second book by Yarmolik and Kachan [<A NAME="[Yarmolik and Kachan, 1993]">
</A>
1993] concentrates on self-test. Books by Lavagno and Sangiovanni-Vincentelli [<A NAME="[Lavagno and Sangiovanni-Vincentelli, 1993]">
</A>
1993] and by Lee [<A NAME="[Lee, 1997]">
</A>
1997] are advanced works on the integration of test synthesis and logic synthesis. The text by Jha and Kundu [<A NAME="[Jha and Kundu, 1990]">
</A>
1990] covers reliability in design. The book by Bhattacharya and Hayes [<A NAME="[Bhattacharya and Hayes, 1990]">
</A>
1990] covers modeling for testing (and includes a good description of the D and PODEM algorithms). There are alternative ASIC test techniques that we have not covered. For example, Chandra’s paper describes the <SPAN CLASS="Definition">
CrossCheck</SPAN>
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architecture for gate arrays [<A NAME="[Chandra, 1993]">
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1993]. A book by Chakradhar, Agrawal, and Bushnell [<A NAME="[Chakradhar, Agrawal, and Bushnell, 1991]">
</A>
1991] covers neural models for testing.</P>
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The major conferences in the area of test are the<SPAN CLASS="Emphasis">
</SPAN>
<A NAME="marker=109151">
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International Test Conference, known as the ITC<A NAME="marker=109091">
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(TK7874.I593, ISSN 0743-1686), the <A NAME="marker=109339">
</A>
International Test Symposium (TK7874.I3274, ISBN depends on year), and the <A NAME="marker=109149">
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European Design and Test Conference (TK7888.4.E968, 1994: ISBN 0-8186-5410-4). The <A NAME="marker=109327">
</A>
IEEE International Workshop on Memory Technology, Design, and Testing (TK7895.M4.I334) is a conference on memory testing. US DoD standard procedure 5012 of Mil-Std-883 sets requirements for simulation algorithms, fault collapsing, undetectable faults, potential detection, and detection strobing (see also <SPAN CLASS="Emphasis">
</SPAN>
<A NAME="marker=109148">
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<SPAN CLASS="BookTitle">
IEEE Design & Test Magazine,</SPAN>
Sept. 1993, pp. 68–79). </P>
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The IEEE has published a series of tutorials on test: <SPAN CLASS="Emphasis">
</SPAN>
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<SPAN CLASS="BookTitle">
VLSI Support Technologies: Computer-Aided Design, Testing, and Packaging,</SPAN>
TK7874.T886, 1982; <SPAN CLASS="Emphasis">
</SPAN>
<A NAME="marker=109267">
</A>
<SPAN CLASS="BookTitle">
VLSI Testing & Validation Techniques,</SPAN>
ISBN 0818606681, TK7874.T8855, 1985; <SPAN CLASS="Emphasis">
</SPAN>
<A NAME="marker=109266">
</A>
<SPAN CLASS="BookTitle">
Test Generation for VLSI Chips,</SPAN>
ISBN 081868786X, TK7874.T8857, 1988. </P>
<P CLASS="Body">
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The <SPAN CLASS="Definition">
Waveform and Vector Exchange Specification</SPAN>
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(<A NAME="marker=109093">
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WAVES<A NAME="marker=109094">
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), <A NAME="marker=109095">
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IEEE Std 1029.1-1991 [<A NAME="[IEEE 1029.1-1991]">
</A>
IEEE 1029.1-1991], is a standard representation for digital stimulus and response for both design and test and allows digital stimulus and response information to be exchanged between different simulation and test tools. The syntax of WAVES is a subset of VHDL. WAVES was developed by the <A NAME="marker=109097">
</A>
WAVES Analysis and Standardization Group (<A NAME="marker=109098">
</A>
WASG<A NAME="marker=109099">
</A>
). The WASG was jointly sponsored by the Automatic Test Program Generation (ATPG) subcommittee of the <A NAME="marker=109100">
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Standards Coordination Committee 20 (<A NAME="marker=109101">
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SCC20) and the <A NAME="marker=109102">
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Design Automation Standards Subcommittee (<A NAME="marker=109103">
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DASS<A NAME="marker=109104">
</A>
) of the Computer Society.</P>
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