ch14.b.htm
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14.12 <A NAME="12927">
</A>
(Finding faults, 30 min.)</P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=113889">
</A>
a. List all the possible stuck-at faults for the circuit in <A HREF="CH14.b.htm#39697" CLASS="XRef">
Figure 14.37</A>
using node faults. </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=113890">
</A>
b. Find all of the equivalent fault classes using node collapsing. </LI>
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<A NAME="pgfId=113891">
</A>
c. List the prime faults. </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=113892">
</A>
d. List all possible stuck-at faults using input and output faults (use A1.B and A2.B to distinguish between different inputs and outputs on the same net). </LI>
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FIGURE 14.37 <A NAME="39697">
</A>
An example circuit for fault collapsing (Problem <A HREF="CH14.b.htm#12927" CLASS="XRef">
14.12</A>
).</P>
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<DIV>
<IMG SRC="CH14-41.gif">
</DIV>
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<LI CLASS="ExercisePart">
<A NAME="pgfId=113893">
</A>
e. List the fault-equivalence classes using gate collapsing. </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=113894">
</A>
f. List the prime faults.</LI>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=74279">
</A>
14.13 (Blind faith, 10 min.) Consider the following code: <SPAN CLASS="BodyComputer">
a = b && f(c)</SPAN>
. Verilog stops executing an expression as soon as it determines that the expression is false, whereas VeriFault does not. What effect does this have?</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=77118">
</A>
14.14 <A NAME="23273">
</A>
(Fault collapsing, 10 min.) Draw the Karnaugh maps including stuck-at faults for four-input NAND, AND, OR, and NOR gates.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=74761">
</A>
14.15 (Fault dominance, 10 min.) If T<SUB CLASS="SubscriptVariable">
x</SUB>
is the set of test vectors that test for fault <SPAN CLASS="EquationVariables">
x</SPAN>
and T<SUB CLASS="SubscriptVariable">
b</SUB>
<SPAN CLASS="Symbol">
Õ</SPAN>
T<SUB CLASS="SubscriptVariable">
a</SUB>
, what can you say about faults <SPAN CLASS="EquationVariables">
a</SPAN>
and <SPAN CLASS="EquationVariables">
b</SPAN>
?</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=98600">
</A>
14.16 (*Fault dominance, 10 min.) Consider the network C = AND (A, B), D = NOT (B). List the PIs, POs, and faults under a pin-fault model. For each fault, state whether it is an equivalent fault, dominant fault, or dominated fault. Now consider this more formal definition of fault dominance: Fault <SPAN CLASS="EquationVariables">
a</SPAN>
dominates <SPAN CLASS="EquationVariables">
b</SPAN>
if and only if <SPAN CLASS="EquationVariables">
a</SPAN>
and <SPAN CLASS="EquationVariables">
b</SPAN>
are equivalent under the set of tests T for <SPAN CLASS="EquationVariables">
b</SPAN>
. Two faults are equivalent under a test T if and only if the circuit response of the two faulty circuits is identical. <SPAN CLASS="Emphasis">
Hint:</SPAN>
Consider the fault at the input of the inverter very carefully.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=124353">
</A>
14.17 (Japanese TVs, 20 min.) As an experiment a Japanese manufacturer decided not to perform any testing of its TVs before turning them on at the end of the production line. They achieved over a 90 percent turn-on rate. Build a cost model for this approach to testing. Make a one-page list of its advantages and disadvantages.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=124354">
</A>
14.18 (Test costs, 20 min.) The CEO of an ASIC vendor called a meeting and asked the production manager to bring all wafers queued for rework. The CEO produced a hammer and smashed the several hundred wafers on the boardroom table. Construct a model around the following assumptions: 2 percent of wafers-in-process currently require rework after each of the 12 photo steps in the process, wafer cost is $2 ,000, 30 percent of the wafer costs are in the photo steps; current process yield is 85 percent, 30 percent of the reworked wafers have to be scrapped. Explain why you were not as shocked by this episode as the production manager and how it helped you to explain to the CEO the need to add time to your ASIC design schedule to include design for test.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=86991">
</A>
14.19 (ZyCAD RP, 10 min.) The ZyCAD Paradigm RP rapid prototyping system consists of a set of emulation boards. Each emulation board contains 18 Xilinx 3090 chips and 16 Xilinx 4010 chips. The Xilinx 4010 chips are mounted on eight daughterboards, and the 3090 chips are mounted directly on the motherboard. The Xilinx 4010 chips are used for logic block emulation and the Xilinx 3090 chips are used for crossbar routing. Each daughterboard has 288 I/O pins that are available to the crossbar chips for routing. Each Xilinx 4010 device has the capability to interface with any other 4010 device on the emulation board. The Xilinx 4010 devices have 400 Configurable Logic Blocks (CLBs) per device and 160 programmable I/O's. Estimate the size of an ASIC that you could prototype with this system.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=73560">
</A>
14.20 (IDDQ testing, 10 min.) In the <SPAN CLASS="Definition">
six-shorts-per-transistor fault model</SPAN>
<A NAME="marker=98627">
</A>
for IDDQ testing we model six shorts per transistor. What are they?</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=9448">
</A>
14.21 <A NAME="33170">
</A>
(PRBS) Consider <A HREF="CH14.b.htm#20055" CLASS="XRef">
Table 14.26</A>
. </P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=119379">
</A>
a. (15 min.) What is the autocorrelation function for a maximal-length pseudorandom binary sequence? </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=119380">
</A>
b. ** (30 min.) Suppose we apply a pseudorandom sequence to a linear system. What is its response? </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=119383">
</A>
c. *** (60 min.) Suppose we correlate this response with the original pseudorandom sequence delayed by <SPAN CLASS="EquationVariables">
n</SPAN>
cycles. What is this correlation function?</LI>
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<A NAME="pgfId=18933">
</A>
TABLE 14.26 <A NAME="20055">
</A>
Autocorrelation of pseudorandom binary sequences (Problem <A HREF="CH14.b.htm#33170" CLASS="XRef">
14.21</A>
).</P>
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<TD ROWSPAN="1" COLSPAN="7">
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<A NAME="pgfId=19114">
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Delay (clock ticks)</P>
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0</P>
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1</P>
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2</P>
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3</P>
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6</P>
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Q2<SUB CLASS="Subscript">
t</SUB>
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Q2<SUB CLASS="Subscript">
t – 1</SUB>
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<A NAME="pgfId=18951">
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Q2<SUB CLASS="Subscript">
t – 2</SUB>
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<A NAME="pgfId=18953">
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Q2<SUB CLASS="Subscript">
t – 3</SUB>
</P>
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<TD ROWSPAN="1" COLSPAN="1">
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