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<H1 CLASS="Heading1">
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14.11 <A NAME="21785">
</A>
Problems</H1>
<P CLASS="Exercise">
<A NAME="pgfId=47182">
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* = Difficult, ** = Very difficult, *** = Extremely difficult</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=78513">
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14.1 (Acronyms, 10 min.) Translate the following excerpt from a MOSIS report: “Chip description: DLX RISC ASIC with DFT, IEEE 1149 BST, and BIST using PRBS LFSR and MISR. Test results: compaction shorted words.” </P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=3341">
</A>
14.2 <A NAME="15933">
</A>
(Economics of defect levels, 15 min.) You are the product manager for a new workstation. You use 10 similar ASICs as the key component in a computer that sells for $10,000 with a profit margin of 20 percent. You buy the ASICs for $10 each, and the shipping defect level is certified to be 0.1 percent by the ASIC vendor. You are having a problem with a large number of field failures, which you have traced to one of the ASICs. In the first nine months of shipment you have sold 49,500 computers, but 51 have failed in the field, 26 due to the ASIC. Finance estimates that all the field failures have cost at least $1 million in revenue and goodwill. You do not have the time, money, or capability to improve your incoming inspection or assembly tests. You estimate the product lifetime is another 18 months, in which time you will sell another 50,000 units at roughly the same price and profit margin. At an emergency meeting, the ASIC vendor’s test engineer proposes to reduce the ASIC defect level to 0.01 percent immediately by improving the test program, but at a cost. You suggest a coffee break. With the information that you have, you have 15 minutes to estimate just how much extra you are prepared to pay for each ASIC.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=72600">
</A>
14.3 <A NAME="25908">
</A>
(Defect level, 10 min.) In a series of experiments a customer of Zycad, which makes hardware fault-simulation accelerators, tested 10,000 parts from a lot with 30 percent yield. Each experiment used a different fraction of the test vector set. Fit the data in <A HREF="CH14.b.htm#33838" CLASS="XRef">
Table 14.24</A>
to a model.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="4">
<P CLASS="TableTitle">
<A NAME="pgfId=73192">
</A>
TABLE 14.24 <A NAME="33838">
</A>
Defect level as a function of fault coverage (Problem <A HREF="CH14.b.htm#25908" CLASS="XRef">
14.3</A>
).</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=73201">
</A>
Fault coverage/%</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=73203">
</A>
Rejects</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=73253">
</A>
Defective parts</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=73243">
</A>
Defect level/%</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=73207">
</A>
50</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=73209">
</A>
6773</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=73255">
</A>
227</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=73245">
</A>
7</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=73213">
</A>
90</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=73215">
</A>
6877</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=73257">
</A>
133</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=73247">
</A>
3</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=73219">
</A>
99</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=73221">
</A>
6910</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=73259">
</A>
90</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=73249">
</A>
1</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=73225">
</A>
99.99</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=73227">
</A>
6997</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=73261">
</A>
3</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=73251">
</A>
0.01</P>
</TD>
</TR>
</TABLE>
<P CLASS="ExerciseHead">
<A NAME="pgfId=9880">
</A>
14.4 <A NAME="33777">
</A>
(Test cost, 5 min.) Suppose, in the example of <A HREF="CH14.1.htm#36678" CLASS="XRef">
Section 14.1</A>
, reducing the bASIC defect level to 0.1 percent added an extra cost of $1 to each part. Now what is the best way to build the system?</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=95044">
</A>
14.5 (Defects, 5 min.) Finding defects in an ASIC is a hard problem. The average defect density for a submicron process is 1 cm<SUP CLASS="Superscript">
–2</SUP>
or less. </P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=113837">
</A>
a. On average how many defects are there on a 1 cm chip? </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=113838">
</A>
b. If the average defect is 1 <SPAN CLASS="Symbol">
l</SPAN>
<SUP CLASS="Superscript">
2</SUP>
, and <SPAN CLASS="Symbol">
l</SPAN>
= 0.25 <SPAN CLASS="Symbol">
m</SPAN>
m, what is defect area/chip area? </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=113839">
</A>
c. Estimate the ratio of needle volume to haystack volume and comment.</LI>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=95067">
</A>
14.6 (Faults and nodes, 10 min.) </P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=113846">
</A>
a. How many faults are there in a circuit with <SPAN CLASS="EquationVariables">
n</SPAN>
nodes? </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=113850">
</A>
b. Considering fanout how many collapsed faults are there? </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=113851">
</A>
c. Estimate how many test cycles a fault simulator needs to find these faults. </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=113852">
</A>
d. With a 10 MHz clock, how long is a 100 k-gate test (with your estimates)? </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=113853">
</A>
e. Using a 100 MHz computer, how long does this fault simulation take? (Assume simulation time is four orders of magnitude slower than real time.)</LI>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=10077">
</A>
14.7 (PRBS, 10 min.) What are the first three patterns for a 4-bit maximal-length LFSR, given a seed of '0001'? <SPAN CLASS="Emphasis">
Hint:</SPAN>
Is there more than one answer?</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=5166">
</A>
14.8 (Test time, 10 min.) </P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=113878">
</A>
a. How long does a 16-bit shift-register test take at a clock speed of 1 MHz? </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=113879">
</A>
b. Estimate how long it takes to test a 64 k-bit static RAM using a walking 1’s (or marching 1’s) pattern.</LI>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=5172">
</A>
14.9 (Test time, 10 min.) A modern production tester costs $5–10 million. This cost is depreciated over the life of the tester (usually five years in the United States due to Internal Revenue Service guidelines). </P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=5182">
</A>
a. If the tester is in use 24 hours a day, 365 days a year, how much does 1 second of test time cost?</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=5185">
</A>
b. If, due to down time (maintenance, operator sick time and so on) a $10 million tester is actually in use 50 percent of the time for chip testing and test time is 2 seconds, how much does test add to the cost of an ASIC?</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=5200">
</A>
c. Suppose the ASIC die is 300 mils on a side, is fabricated on a 6-inch wafer whose fabrication cost is $1750, and the yield is 68 percent. What is the fraction of test cost to total die cost (fabrication plus test costs)? Assume that the number of die per wafer is equal to wafer area divided by chip area.</LI>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=5167">
</A>
14.10 <A NAME="25160">
</A>
(Fault collapsing, 10 min.) Draw up tables to show how input and output faults collapse using gate collapsing for the following primitive logic gates: AND, OR, NAND, NOR, and EXOR (assume two-input logic cells in each case with inputs A, B and output F); a two-input MUX (inputs S0, S1, and SEL0; output F).</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=4920">
</A>
14.11 <A NAME="22199">
</A>
(Fault simulation, 15 min.) Mentor Graphic Corporation’s QuickFault concurrent fault simulator uses a 12-state logic system with three logic values ('0', '1', 'X') and four strengths (strong = S, resistive = R, high impedance = Z, I = indeterminate). Complete <A HREF="CH14.b.htm#19579" CLASS="XRef">
Table 14.25</A>
using D = detected fault, P = possibly detected fault, and '–' = undetected fault. Give two values, 1/2, for each cell: The first value is for the default fault model in which a tester cannot tell the difference between Z/S/R; the second value is for testers that can differentiate between Z and S/R. <SPAN CLASS="Emphasis">
Hint:</SPAN>
One line of the table has been completed as an example.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="14">
<P CLASS="TableTitle">
<A NAME="pgfId=8888">
</A>
TABLE 14.25 <A NAME="17592">
</A>
<A NAME="19579">
</A>
The logic system used by Mentor Graphic Corporation’s fault simulator, QuickFault (Problem <A HREF="CH14.b.htm#22199" CLASS="XRef">
14.11</A>
).<A HREF="#pgfId=119203" CLASS="footnote">
1</A>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8916">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="13">
<P CLASS="Table">
<A NAME="pgfId=8918">
</A>
<SPAN CLASS="TableHeads">
Faulty circuit</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8944">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8946">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8948">
</A>
<SPAN CLASS="TableHeads">
0I</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8950">
</A>
<SPAN CLASS="TableHeads">
XI</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8952">
</A>
<SPAN CLASS="TableHeads">
1I</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8954">
</A>
<SPAN CLASS="TableHeads">
0Z</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8956">
</A>
<SPAN CLASS="TableHeads">
XZ</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8958">
</A>
<SPAN CLASS="TableHeads">
1Z</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8960">
</A>
<SPAN CLASS="TableHeads">
0R</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8962">
</A>
<SPAN CLASS="TableHeads">
XR</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8964">
</A>
<SPAN CLASS="TableHeads">
1R</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8966">
</A>
<SPAN CLASS="TableHeads">
0S</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8968">
</A>
<SPAN CLASS="TableHeads">
XS</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8970">
</A>
<SPAN CLASS="TableHeads">
1S</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="12" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8972">
</A>
<SPAN CLASS="TableHeads">
Good circuit</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8974">
</A>
<SPAN CLASS="TableHeads">
0I</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8976">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8978">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8980">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8982">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8984">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8986">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8988">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8990">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8992">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8994">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8996">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8998">
</A>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=9002">
</A>
<SPAN CLASS="TableHeads">
XI</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=9004">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=9006">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=9008">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=9010">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
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