ch14.htm
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<P>[ <A HREF="../../ASICs.htm#anchor749424">Chapter Index</A> ] [ <A HREF="CH14.1.htm">Next page</A> ]</P><!--#include file="AmazonAsic.html"--><HR></DIV>
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TEST</H1>
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ASICs are tested at two stages during manufacture using <SPAN CLASS="Definition">
production tests</SPAN>
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. First, the silicon die are tested after fabrication is complete at <SPAN CLASS="Definition">
wafer test</SPAN>
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or <SPAN CLASS="Definition">
wafer sort</SPAN>
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. Each wafer is tested, one die at a time, using an array of probes on a <SPAN CLASS="Definition">
probe card</SPAN>
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that descend onto the bonding pads of a single die. The <SPAN CLASS="Definition">
production tester</SPAN>
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applies signals generated by a <SPAN CLASS="Definition">
test program</SPAN>
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and measures the ASIC <SPAN CLASS="Definition">
test response</SPAN>
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. A test program often generates hundreds of thousands of different <SPAN CLASS="Definition">
test vectors</SPAN>
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applied at a frequency of several megahertz over several hundred milliseconds. Chips that fail are automatically marked with an ink spot. Production testers are large machines that take up their own room and are very expensive (typically well over $1 million). Either the customer, or the ASIC manufacturer, or both, develops the test program.</P>
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A diamond saw separates the die, and the good die are bonded to a lead carrier and packaged. A second, <SPAN CLASS="Definition">
final test</SPAN>
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is carried out on the packaged ASIC (usually with the same test vectors used at wafer sort) before the ASIC is shipped to the customer. The customer may apply a <SPAN CLASS="Definition">
goods-inward test</SPAN>
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to incoming ASICs if the customer has the resources and the product volume is large enough. Normally, though, parts are directly assembled onto a bare <SPAN CLASS="Definition">
printed-circuit board</SPAN>
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PCB</SPAN>
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or <SPAN CLASS="Definition">
board</SPAN>
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) and then the board is tested. If the board test shows that an ASIC is bad at this point, it is difficult to replace a surface-mounted component soldered on the board, for example. If there are several board failures due to a particular ASIC, the board manufacturer typically ships the defective chips back to the ASIC vendor. ASIC vendors have sophisticated <SPAN CLASS="Definition">
failure analysis</SPAN>
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departments that take packaged ASICs apart and can often determine the failure mechanism. If the ASIC production tests are adequate, failures are often due to the soldering process, electrostatic damage during handling, or other problems that can occur between the part being shipped and board test. If the problem is traced to defective ASIC fabrication, this indicates that the test program may be inadequate. As we shall see, failure and diagnosis at the board level is very expensive. Finally, ASICs may be tested and replaced (usually by swapping boards) either by a customer who buys the final product or by servicing—this is <SPAN CLASS="Definition">
field repair</SPAN>
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. Such system-level diagnosis and repair is even more expensive.</P>
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Programmable ASICs (including FPGAs) are a special case. Each programmable ASIC is tested to the point that the manufacturer can guarantee with a high degree of confidence that if your design works, and if you program the FPGA correctly, then your ASIC will work. Production testing is easier for some programmable ASIC architectures than others. In a reprogrammable technology the manufacturer can test the programming features. This cannot be done for a one-time programmable antifuse technology, for example. A programmable ASIC is still tested in a similar fashion to any other ASIC and you are still paying for test development and design. Programmable ASICs also have similar test, defect, and manufacturing problems to other members of the ASIC family. Finally, once a programmable ASIC is soldered to a board and part of a system, it looks just like any other ASIC. As you will see in the next section, considering board-level and system-level testing is a very important part of ASIC design.</P>
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<H1 CLASS="Heading1TOC">
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14.1 The Importance of Test</A>
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14.2 Boundary-Scan Test</A>
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14.3 Faults</A>
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14.4 Fault Simulation</A>
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14.5 Automatic Test-Pattern Generation</A>
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14.6 Scan Test</A>
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14.7 Built-in Self-test</A>
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14.8 A Simple Test Example</A>
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14.9 The Viterbi Decoder Example</A>
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14.10 <SPAN CLASS="BodyComputer">
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Summary</A>
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14.11 Problems</A>
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14.12 Bibliography</A>
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14.13 References</A>
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<HR><P>[ <A A HREF="../../ASICs.htm#anchor749424">Chapter Index</A> ] [ <A HREF="CH14.1.htm">Next page</A> ]</P></BODY>
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