📄 ch14.4.htm
字号:
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=117539">
</A>
0</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=117543">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=117545">
</A>
F6</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=117547">
</A>
SA1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=117549">
</A>
7</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=117551">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=117553">
</A>
0</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=117557">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=117559">
</A>
F7</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=117561">
</A>
SA1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=117563">
</A>
0, 1, 3, 4, 5</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=117565">
</A>
0, 0, 0, 0, 0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=117567">
</A>
1, 1, 1, 1, 1</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=117571">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=117573">
</A>
F8</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=117575">
</A>
SA0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=117577">
</A>
2, 6, 7</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=117579">
</A>
1, 1, 1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=117581">
</A>
0, 0, 0</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=117586">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="5">
<P CLASS="TableLeft">
<A NAME="pgfId=118470">
</A>
<SUP CLASS="Superscript">
1</SUP>
Test vector format:</P>
<P CLASS="TableLeft">
<A NAME="pgfId=118471">
</A>
<SPAN CLASS="Bold">
3</SPAN>
= 011, so that CBA = 011: C = '0', B = '1', A = '1'</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="6">
<P CLASS="TableLeft">
<A NAME="pgfId=117600">
</A>
</P>
<P CLASS="TableLeft">
<A NAME="pgfId=117602">
</A>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="7">
<P CLASS="TableFigTitleSide">
<A NAME="pgfId=118448">
</A>
FIGURE 14.16 <A NAME="42019">
</A>
Fault simulation of A'B + BC. The simulation results for fault F1 (U2 output stuck at 1) with test vector value hex <SPAN CLASS="Bold">
3</SPAN>
(shown in bold in the table) are shown on the LogicWorks schematic. Notice that the output of U2 is 0 in the good circuit and stuck at 1 in the bad circuit.</P>
</TD>
</TR>
</TABLE>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=75828">
</A>
14.4.8 A Fault-Simulation Example</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=118011">
</A>
<A HREF="CH14.4.htm#42019" CLASS="XRef">
Figure 14.16</A>
illustrates fault simulation using the circuit of <A HREF="CH14.3.htm#16029" CLASS="XRef">
Figure 14.14</A>
. We have used all possible inputs as a test vector set in the following order: <SPAN CLASS="BodyComputer">
{000, 001, 010, 011, 100, 101, 110, 111}</SPAN>
. There are eight collapsed SSFs in this circuit, F1–F8. Since the good circuit is irredundant, we have 100 percent fault coverage. The following fault-simulation results were derived from a logic simulator rather than a fault simulator, but are presented in the same format as output from an automated test system. </P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=118015">
</A>
Total number of faults: 22</P>
<P CLASS="Computer">
<A NAME="pgfId=77628">
</A>
Number of faults in collapsed fault list: 8</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=78013">
</A>
Test Vector Faults detected Coverage/% Cumulative/%</P>
<P CLASS="Computer">
<A NAME="pgfId=78014">
</A>
----------- --------------- ---------- ------------</P>
<P CLASS="Computer">
<A NAME="pgfId=78048">
</A>
000 F2, F7 25.0 25.0</P>
<P CLASS="Computer">
<A NAME="pgfId=78062">
</A>
001 F7 12.5 25.0</P>
<P CLASS="Computer">
<A NAME="pgfId=78068">
</A>
010 F5, F8 25.0 62.5</P>
<P CLASS="Computer">
<A NAME="pgfId=78053">
</A>
011 F1, F4, F7 37.5 75.0</P>
<P CLASS="Computer">
<A NAME="pgfId=78056">
</A>
100 F2, F3, F7 37.5 87.5</P>
<P CLASS="Computer">
<A NAME="pgfId=78083">
</A>
101 F3, F7 25.0 87.5</P>
<P CLASS="Computer">
<A NAME="pgfId=78084">
</A>
110 F8 12.5 100.0</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=78085">
</A>
111 F6, F8 25.0 100.0</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=77642">
</A>
Total number of vectors : 8</P>
<P CLASS="Computer">
<A NAME="pgfId=77645">
</A>
Noncollapsed Collapsed</P>
<P CLASS="Computer">
<A NAME="pgfId=77711">
</A>
Fault counts:</P>
<P CLASS="Computer">
<A NAME="pgfId=77713">
</A>
Detected 16 8</P>
<P CLASS="Computer">
<A NAME="pgfId=77649">
</A>
Untested 0 0</P>
<P CLASS="Computer">
<A NAME="pgfId=77650">
</A>
------ ------</P>
<P CLASS="Computer">
<A NAME="pgfId=77651">
</A>
Detectable 16 8 </P>
<P CLASS="Computer">
<A NAME="pgfId=77653">
</A>
</P>
<P CLASS="Computer">
<A NAME="pgfId=77978">
</A>
Redundant 0 0</P>
<P CLASS="Computer">
<A NAME="pgfId=77654">
</A>
Tied 0 0</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=77975">
</A>
FAULT COVERAGE 100.00 % 100.00 %</P>
<P CLASS="Body">
<A NAME="pgfId=77624">
</A>
Fault simulation tells us that we need to apply seven test vectors in order to achieve full fault coverage. The highest-quality test vectors are <SPAN CLASS="BodyComputer">
{011}</SPAN>
and <SPAN CLASS="BodyComputer">
{100}</SPAN>
. For example, test vector <SPAN CLASS="BodyComputer">
{011}</SPAN>
detects three faults (F1, F4, and F7) out of eight. This means if we were to reduce the test set to just <SPAN CLASS="BodyComputer">
{011}</SPAN>
the fault coverage would be 3/8, or 37 percent. Proceeding in this fashion we reorder the test vectors in terms of their contribution to cumulative test coverage as follows: <SPAN CLASS="BodyComputer">
{011, 100, 010, 111, 000, 001, 101, 110}</SPAN>
. This is a hard problem for large numbers of test vectors because of the interdependencies between the faults detected by the different vectors. Repeating the fault simulation gives the following fault grading:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=78110">
</A>
Test Vector Faults detected Coverage/% Cumulative/%</P>
<P CLASS="Computer">
<A NAME="pgfId=78111">
</A>
----------- --------------- ---------- ------------</P>
<P CLASS="Computer">
<A NAME="pgfId=78125">
</A>
011 F1, F4, F7 37.5 37.5</P>
<P CLASS="Computer">
<A NAME="pgfId=78135">
</A>
100 F2, F3, F7 37.5 62.5</P>
<P CLASS="Computer">
<A NAME="pgfId=78145">
</A>
010 F5, F8 25.0 87.5</P>
<P CLASS="Computer">
<A NAME="pgfId=78153">
</A>
111 F6, F8 25.0 100.0</P>
<P CLASS="Computer">
<A NAME="pgfId=78112">
</A>
000 F2, F7 25.0 100.0</P>
<P CLASS="Computer">
<A NAME="pgfId=78113">
</A>
001 F7 12.5 100.0</P>
<P CLASS="Computer">
<A NAME="pgfId=78117">
</A>
101 F3, F7 25.0 100.0</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=78118">
</A>
110 F8 12.5 100.0</P>
<P CLASS="Body">
<A NAME="pgfId=78107">
</A>
Now, instead of using seven test vectors, we need only apply the first four vectors from this set to achieve 100 percent fault coverage, cutting the expensive production test time nearly in half. Reducing the number of test vectors in this fashion is called <SPAN CLASS="Definition">
test-vector compression</SPAN>
<A NAME="marker=78467">
</A>
or <SPAN CLASS="Definition">
test-vector compaction</SPAN>
<A NAME="marker=78468">
</A>
.</P>
<P CLASS="Body">
<A NAME="pgfId=78205">
</A>
The fault signatures for faults F1–F8 for the last test sequence, <SPAN CLASS="BodyComputer">
{011, 100, 010, 111, 000, 001, 101, 110}</SPAN>
, are as follows:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=79200">
</A>
# fail good bad</P>
<P CLASS="Computer">
<A NAME="pgfId=80956">
</A>
-- ---- ---- -------- --------</P>
<P CLASS="Computer">
<A NAME="pgfId=80949">
</A>
F1 10000000 00110001 10110001</P>
<P CLASS="Computer">
<A NAME="pgfId=79201">
</A>
F2 01001000 00110001 01111001</P>
<P CLASS="Computer">
<A NAME="pgfId=79202">
</A>
F3 01000010 00110001 01110011</P>
<P CLASS="Computer">
<A NAME="pgfId=79203">
</A>
F4 10000000 00110001 10110001</P>
<P CLASS="Computer">
<A NAME="pgfId=79204">
</A>
F5 00100000 00110001 00010001</P>
<P CLASS="Computer">
<A NAME="pgfId=79205">
</A>
F6 00010000 00110001 00100001</P>
<P CLASS="Computer">
<A NAME="pgfId=79206">
</A>
F7 11001110 00110001 11111111</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=78214">
</A>
F8 00110001 00110001 00000000 </P>
<P CLASS="Body">
<A NAME="pgfId=78215">
</A>
The first pattern for each fault indicates which test vectors will fail on the tester (we say a test vector fails when it successfully detects a faulty circuit during a production test). Thus, for fault F1, pattern <SPAN CLASS="BodyComputer">
'10000000'</SPAN>
indicates that only the first test vector will fail if fault F1 is present. The second and third patterns for each fault are the POs of the good and bad circuits for each test vector. Since we only have one PO in our simple example, these patterns do not help further distinguish between faults. Notice, that as far as an external view is concerned, faults F1 and F4 have identical fault signatures and are therefore indistinguishable. Faults F1 and F4 are said to be <SPAN CLASS="Definition">
structurally equivalent</SPAN>
<A NAME="marker=81039">
</A>
. In general, we cannot detect structural equivalence by looking at the circuit. If we apply only the first four test vectors, then faults F2 and F3 also have identical fault signatures. Fault signatures are only useful in diagnosing fault locations if we have one, or a very few faults.</P>
<P CLASS="Body">
<A NAME="pgfId=78257">
</A>
Not all fault simulators give all the information we have described. Most fault simulators drop hard-detected faults from consideration once they are detected to increase the speed of simulation. With dropped hard-detected faults we cannot independently grade each vector and we cannot construct a fault dictionary. This is the reason we used a logic simulator to generate the preceding results.</P>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=74257">
</A>
14.4.9 Fault Simulation in an ASIC Design Flow</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=74258">
</A>
At the beginning of this section we dodged the issue of test-vector generation. It is possible to automatically generate test vectors and test programs (with certain restrictions), and we shall discuss these methods in <A HREF="CH14.5.htm#41037" CLASS="XRef">
Section 14.5</A>
. A by-product of some of these automated systems is a measure of fault coverage. However, fault simulation is still used for the following reasons:</P>
<UL>
<LI CLASS="BulletFirst">
<A NAME="pgfId=75571">
</A>
Test-generation software is expensive, and many designers still create test programs manually and then grade the test vectors using fault simulation.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=74259">
</A>
Automatic test programs are not yet at the stage where fault simulation can be completely omitted in an ASIC design flow. Usually we need fault simulation to add some vectors to test logic not covered automatically, to check that test logic has been inserted correctly, or to understand and correct fault coverage problems.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=75606">
</A>
It is far too expensive to use a production tester to debug a production test. One use of a fault simulator is to perform this function off line.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=74261">
</A>
The reuse and automatic generation of large cells is essential to decrease the complexity of large ASIC designs. Megacells and embedded blocks (an embedded microcontroller, for example) are normally provided with <SPAN CLASS="Definition">
canned test vectors </SPAN>
<A NAME="marker=75637">
</A>
that have already been fault simulated and fault graded. The megacell has to be isolated during test to apply these vectors and measure the response. Cell compilers for RAM, ROM, multipliers, and other regular structures may also generate test vectors. Fault simulation is one way to check that the various embedded blocks and their vectors have been correctly glued together with the rest of the ASIC to produce a complete set of test vectors and a test program.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=74260">
</A>
Production testers are very expensive. There is a trend away from the use of test vectors to include more of the test function on an ASIC. Some internal test logic structures generate test vectors in a random or pseudorandom fashion. For these structures there is no known way to generate the fault coverage. For these types of test structures we will need some type of fault simulation to measure fault coverage and estimate defect levels.</LI>
</UL>
</DIV>
<HR>
<DIV CLASS="footnotes">
<DIV CLASS="footnote">
<P CLASS="TableFootLast">
<SPAN CLASS="footnoteNumber">
1.</SPAN>
<A NAME="pgfId=75380">
</A>
L = 0 or Z; H = 1 or Z; Z = high impedance; X = unknown; D = detected; P = potentially detected; U = undetected.</P>
</DIV>
</DIV>
<HR><P>[ <A HREF="CH14.htm">Chapter start</A> ] [ <A HREF="CH14.3.htm">Previous page</A> ] [ <A HREF="CH14.5.htm">Next page</A> ]</P></BODY>
<!--#include file="Copyright.html"--><!--#include file="footer.html"-->
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -