ch14.4.htm

介绍asci设计的一本书

<SPAN CLASS="Definition">
uncontrollable nets</SPAN>
 and <A NAME="marker=53683">
 </A>
<SPAN CLASS="Definition">
unobservable nets</SPAN>
 result in faults we cannot detect. We call these faults <SPAN CLASS="Definition">
untested faults</SPAN>
<A NAME="marker=74407">
 </A>
, <A NAME="marker=53685">
 </A>
<SPAN CLASS="Definition">
untestable faults</SPAN>
, or <A NAME="marker=53686">
 </A>
<SPAN CLASS="Definition">
impossible faults</SPAN>
. </P>
<P CLASS="Body">
<A NAME="pgfId=53687">
 </A>
If a PO of the good circuit is the opposite to that of the faulty circuit, we have a detected fault (sometimes called a <A NAME="marker=53688">
 </A>
<SPAN CLASS="Definition">
hard-detected fault</SPAN>
 or a <A NAME="marker=53689">
 </A>
<SPAN CLASS="Definition">
definitely detected fault</SPAN>
). If the POs of the good circuit and faulty circuit are identical, we have an <SPAN CLASS="Definition">
undetected fault</SPAN>
<A NAME="marker=56080">
 </A>
. If a PO of the good circuit is a <SPAN CLASS="BodyComputer">
'1'</SPAN>
 or a <SPAN CLASS="BodyComputer">
'0'</SPAN>
 but the corresponding PO of the faulty circuit is an <SPAN CLASS="BodyComputer">
'X'</SPAN>
 (unknown, either <SPAN CLASS="BodyComputer">
'0'</SPAN>
 or <SPAN CLASS="BodyComputer">
'1'</SPAN>
), we have a <A NAME="marker=53691">
 </A>
<SPAN CLASS="Definition">
possibly detected fault</SPAN>
 (<A NAME="marker=53692">
 </A>
also called a <SPAN CLASS="Definition">
possible-detected fault</SPAN>
, <A NAME="marker=53693">
 </A>
<SPAN CLASS="Definition">
potential fault</SPAN>
, or <A NAME="marker=53694">
 </A>
<SPAN CLASS="Definition">
potentially detected fault</SPAN>
). </P>
<P CLASS="Body">
<A NAME="pgfId=53853">
 </A>
If the PO of the good circuit changes between a <SPAN CLASS="BodyComputer">
'1'</SPAN>
 and a <SPAN CLASS="BodyComputer">
'0'</SPAN>
 while the faulty circuit remains at <SPAN CLASS="BodyComputer">
'X'</SPAN>
, then we have a <A NAME="marker=53854">
 </A>
<SPAN CLASS="Definition">
soft-detected fault</SPAN>
. Soft-detected faults are a subset of possibly detected faults. Some simulators keep track of these soft-detected faults separately. Soft-detected faults are likely to be detected on a real tester if this sequence occurs often. Most fault simulators allow you to set a <A NAME="marker=53855">
 </A>
<SPAN CLASS="Definition">
fault-drop threshold</SPAN>
 so that the simulator will remove faults from further consideration after soft-detecting or possibly detecting them a specified number of times. This is called <SPAN CLASS="Definition">
fault dropping</SPAN>
<A NAME="marker=78283">
 </A>
 (or <SPAN CLASS="Definition">
fault discarding</SPAN>
<A NAME="marker=79515">
 </A>
). The more often a fault is possibly detected, the more likely it is to be detected on a real tester.</P>
<P CLASS="Body">
<A NAME="pgfId=53875">
 </A>
A <SPAN CLASS="Definition">
redundant fault</SPAN>
<A NAME="marker=74754">
 </A>
 is a fault that makes no difference to the circuit operation. A combinational circuit with no such faults is <SPAN CLASS="Definition">
irredundant</SPAN>
<A NAME="marker=74760">
 </A>
. There are close links between logic-synthesis algorithms and redundancy. Logic-synthesis algorithms can produce combinational logic that is irredundant and 100 % testable for single stuck-at faults by removing redundant logic as part of logic minimization.</P>
<P CLASS="Body">
<A NAME="pgfId=74890">
 </A>
If a fault causes a circuit to oscillate, it is an <A NAME="marker=74889">
 </A>
<SPAN CLASS="Definition">
oscillatory fault</SPAN>
. Oscillation can occur within feedback loops in combinational circuits with zero-delay models. A fault that affects a larger than normal portion of the circuit is a <A NAME="marker=74891">
 </A>
<SPAN CLASS="Definition">
hyperactive fault</SPAN>
. Fault simulators have settings to prevent such faults from using excessive amounts of computation time. It is very annoying to run a fault simulation for several days only to discover that the entire time was taken up by simulating a single fault in a RS flip-flop or on the clock net, for example. <A HREF="CH14.4.htm#31609" CLASS="XRef">
Figure&nbsp;14.15</A>
 shows some examples of fault categories.</P>
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<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=78192">
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<IMG SRC="CH14-16.gif" ALIGN="BASELINE">
&nbsp;</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=78195">
 </A>
FIGURE&nbsp;14.15&nbsp;<A NAME="31609">
 </A>
Fault categories. (a)&nbsp;A detectable fault requires the ability to control and observe the fault origin. (b)&nbsp;A net that is fixed in value is uncontrollable and therefore will produce one undetected fault. (c)&nbsp;Any net that is unconnected is unobservable and will produce undetected faults. (d)&nbsp;A net that produces an unknown 'X' in the faulty circuit and a '1' or a '0' in the good circuit may be detected (depending on whether the 'X' is in fact a '0' or '1'), but we cannot say for sure. At some point this type of fault is likely to produce a discrepancy between good and bad circuits and will eventually be detected. (e)&nbsp;A redundant fault does not affect the operation of the good circuit. In this case the AND gate is redundant since AB + B' = A + B'.</P>
</TD>
</TR>
</TABLE>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=74860">
 </A>
14.4.6&nbsp;Fault-Simulator Logic Systems</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=74899">
 </A>
In addition to the way the fault simulator counts faults in various fault categories, the number of detected faults during fault simulation also depends on the logic system used by the fault simulator. As an example, Cadence&#8217;s <A NAME="marker=74898">
 </A>
VeriFault concurrent fault simulator uses a logic system with the six logic values: <SPAN CLASS="BodyComputer">
'0'</SPAN>
, <SPAN CLASS="BodyComputer">
'1'</SPAN>
, <SPAN CLASS="BodyComputer">
'Z'</SPAN>
, <SPAN CLASS="BodyComputer">
'L'</SPAN>
, <SPAN CLASS="BodyComputer">
'H'</SPAN>
, <SPAN CLASS="BodyComputer">
'X'</SPAN>
. <A HREF="CH14.4.htm#35605" CLASS="XRef">
Table&nbsp;14.8</A>
 shows the results of comparing the faulty and the good circuit simulations. </P>
<P CLASS="Body">
<A NAME="pgfId=78169">
 </A>
From <A HREF="CH14.4.htm#35605" CLASS="XRef">
Table&nbsp;14.8</A>
 we can deduce that, in this logic system:</P>
<UL>
<LI CLASS="BulletFirst">
<A NAME="pgfId=75087">
 </A>
Fault detection is possible only if the good circuit and the bad circuit both produce either a <SPAN CLASS="BodyComputer">
'1'</SPAN>
 or a <SPAN CLASS="BodyComputer">
'0'</SPAN>
. </LI>
<LI CLASS="BulletList">
<A NAME="pgfId=75096">
 </A>
If the good circuit produces a <SPAN CLASS="BodyComputer">
'Z'</SPAN>
 at a three-state output, no faults can be detected (not even a fault on the three-state output).</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=75099">
 </A>
If the good circuit produces anything other than a <SPAN CLASS="BodyComputer">
'1'</SPAN>
 or <SPAN CLASS="BodyComputer">
'0'</SPAN>
, no faults can be detected.</LI>
</UL>
<P CLASS="Body">
<A NAME="pgfId=74395">
 </A>
A fault simulator assigns faults to each of the categories we have described. We define the fault coverage as:  </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqn">
<A NAME="pgfId=134669">
 </A>
fault coverage = detected faults / detectable faults.</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=134671">
 </A>
(14.2)</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=134920">
 </A>
The number of detectable faults excludes any undetectable fault categories (untestable or redundant faults). Thus,   </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqn">
<A NAME="pgfId=134923">
 </A>
detectable faults = faults &#8211; undetectable faults,</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=134925">
 </A>
(14.3)</P>
</TD>
</TR>
</TABLE>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqn">
<A NAME="pgfId=134932">
 </A>
undetectable faults = untested faults + redundant faults.</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=134934">
 </A>
(14.4)</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=75365">
 </A>
The fault simulator may also produce an analysis of <A NAME="marker=75364">
 </A>
<SPAN CLASS="Definition">
fault grading</SPAN>
. This is a graph, histogram, or tabular listing showing the cumulative fault coverage as a function of the number of test vectors. This information is useful to remove <A NAME="marker=75366">
 </A>
<SPAN CLASS="Definition">
dead test cycles</SPAN>
, which contain vectors that do not add to fault coverage. If you reinitialize the circuit at regular intervals, you can remove vectors up to an initialization without altering the function of any vectors after the initialization. The list of faults that the simulator inserted is the <A NAME="marker=75367">
 </A>
<SPAN CLASS="Definition">
fault list. </SPAN>
In addition to the fault list, a <A NAME="marker=75368">
 </A>
<SPAN CLASS="Definition">
fault dictionary</SPAN>
 lists the faults with their corresponding primary outputs (the <A NAME="marker=75369">
 </A>
<SPAN CLASS="Definition">
faulty output vector</SPAN>
). The set of input vectors and faulty output vectors that uniquely identify a fault is the <A NAME="marker=75370">
 </A>
<SPAN CLASS="Definition">
fault signature</SPAN>
. This information can be useful to test engineers, allowing them to work backward from production test results and pinpoint the cause of a problem if several ASICs fail on the tester for the same reasons. </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="8">
<P CLASS="TableTitle">
<A NAME="pgfId=75381">
 </A>
TABLE&nbsp;14.8&nbsp;<A NAME="31274">
 </A>
<A NAME="35605">
 </A>
The VeriFault concurrent fault simulator logic system.<A HREF="#pgfId=75380" CLASS="footnote">
1</A>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=75397">
 </A>
&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=75399">
 </A>
&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="6">
<P CLASS="Table">
<A NAME="pgfId=75401">
 </A>
<SPAN CLASS="TableHeads">
Faulty circuit </SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=75413">
 </A>
&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=75415">
 </A>
&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=75417">
 </A>
<SPAN CLASS="TableHeads">
0</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=75419">
 </A>
<SPAN CLASS="TableHeads">
1</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=75421">
 </A>
<SPAN CLASS="TableHeads">
Z</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=75423">
 </A>
<SPAN CLASS="TableHeads">
L</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=75425">
 </A>
<SPAN CLASS="TableHeads">
H</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=75427">
 </A>
<SPAN CLASS="TableHeads">
X</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="6" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=75429">
 </A>
<SPAN CLASS="TableHeads">
Good circuit</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=75431">
 </A>
<SPAN CLASS="TableHeads">
0</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=75433">
 </A>
U</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=75435">
 </A>
D</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=75437">
 </A>
P</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=75439">
 </A>
P</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=75441">
 </A>
P</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=75443">
 </A>
P</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=75447">
 </A>
<SPAN CLASS="TableHeads">
1</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=75449">
 </A>
D</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=75451">
 </A>
U</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=75453">
 </A>
P</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=75455">
 </A>
P</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">