ch09.1.htm

介绍asci设计的一本书

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FIGURE&nbsp;9.4&nbsp;<A NAME="29121">
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A cell and its subschematic. (a)&nbsp;A schematic library containing icons for the primitive cells. (b)&nbsp;A subschematic for a cell, DLAT, showing the instance names for the primitive cells. (c)&nbsp;A symbol for cell DLAT.</P>
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<A HREF="#42193" CLASS="XRef">
Figure&nbsp;9.5</A>
(a) shows a more complex subschematic for a 4-bit latch. Each primitive cell instance in this schematic must have a unique name. This can get very tiresome for large circuits. Instead of creating complex, but repetitive, subschematics for complex cells we can use hierarchy. </P>
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FIGURE&nbsp;9.5&nbsp;<A NAME="42193">
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A 4-bit latch: (a)&nbsp;drawn as a flat schematic from gate-level primitives, (b)&nbsp;drawn as four instances of the cell symbol DLAT, (c)&nbsp;drawn using a vectored instance of the DLAT cell symbol with cardinality of 4, (d)&nbsp;drawn using a new cell symbol with cell name FourBit.</P>
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<A NAME="pgfId=29586">
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<A HREF="#42193" CLASS="XRef">
Figure&nbsp;9.5</A>
(b) shows a hierarchical subschematic for a cell <SPAN CLASS="BodyComputer">
FourBit</SPAN>
, which in turn uses four instances of the cell <SPAN CLASS="BodyComputer">
DLAT</SPAN>
. The four instances of <SPAN CLASS="BodyComputer">
DLAT</SPAN>
 in <A HREF="#42193" CLASS="XRef">
Figure&nbsp;9.5</A>
(b) have different instance names: <SPAN CLASS="BodyComputer">
L1</SPAN>
,<SPAN CLASS="BodyComputer">
 L2</SPAN>
,<SPAN CLASS="BodyComputer">
 L3</SPAN>
, and <SPAN CLASS="BodyComputer">
L4</SPAN>
. Notice that we cannot use just one name for the four instances of <SPAN CLASS="BodyComputer">
DLAT</SPAN>
 to indicate that they are all the same cell. If we did, we could not differentiate between <SPAN CLASS="BodyComputer">
L1</SPAN>
 and <SPAN CLASS="BodyComputer">
L2</SPAN>
, for example. </P>
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<A NAME="pgfId=29498">
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The vertical row of instances in <A HREF="#42193" CLASS="XRef">
Figure&nbsp;9.5</A>
(b) looks like a vector of elements. <A HREF="#42193" CLASS="XRef">
Figure&nbsp;9.5</A>
(c) shows a <SPAN CLASS="Definition">
vectored instance</SPAN>
<A NAME="marker=29506">
 </A>
 representing four copies of the <SPAN CLASS="BodyComputer">
DLAT</SPAN>
 cell. We say the <SPAN CLASS="Definition">
cardinality</SPAN>
<A NAME="marker=29510">
 </A>
 of this instance is 4. Tools normally use bold lines or some other distinguishing feature to represent a vectored instance. The cardinality information is often shown as a vector. Thus <SPAN CLASS="BodyComputer">
L[1:4]</SPAN>
 represents four instances: <SPAN CLASS="BodyComputer">
L[1]</SPAN>
, <SPAN CLASS="BodyComputer">
L[2]</SPAN>
, <SPAN CLASS="BodyComputer">
L[3]</SPAN>
, <SPAN CLASS="BodyComputer">
L[4]</SPAN>
. This is convenient because now we can see that all subcells are identical copies of <SPAN CLASS="BodyComputer">
L</SPAN>
, but we have a unique name for each.</P>
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<A NAME="pgfId=29518">
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Finally, as shown in <A HREF="#42193" CLASS="XRef">
Figure&nbsp;9.5</A>
(d) we can create a new symbol for the 4-bit latch, <SPAN CLASS="BodyComputer">
FourBit</SPAN>
. The symbol for <SPAN CLASS="BodyComputer">
FourBit</SPAN>
 has a 4-bit-wide input bus for the four D inputs, and a 4-bit wide output bus for the four Q outputs. The subschematic for <SPAN CLASS="BodyComputer">
FourBit </SPAN>
could be either <A HREF="#42193" CLASS="XRef">
Figure&nbsp;9.5</A>
(a), (b), or (c) (though the exact naming of the inputs and outputs and their attachment to the buses may be different in each case).</P>
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We need a convention to distinguish, for example, between the inverter subcells, <SPAN CLASS="BodyComputer">
inv1</SPAN>
, which are children of the cell <SPAN CLASS="BodyComputer">
DLAT</SPAN>
, which are in turn children of the cell <SPAN CLASS="BodyComputer">
FourBit</SPAN>
. Most schematic-entry tools do this by combining the instance names of the subcells in a hierarchical manner using a special character as a delimiter. For example, if we drew the subschematic as in <A HREF="#42193" CLASS="XRef">
Figure&nbsp;9.5</A>
(b), the four inverters in <SPAN CLASS="BodyComputer">
FourBit</SPAN>
 might be named <SPAN CLASS="BodyComputer">
L1.inv1</SPAN>
,<SPAN CLASS="BodyComputer">
 L2.inv1</SPAN>
,<SPAN CLASS="BodyComputer">
 L3.inv1</SPAN>
, and <SPAN CLASS="BodyComputer">
L4.inv1</SPAN>
. Once again this makes it clear that the inverters, <SPAN CLASS="BodyComputer">
inv1</SPAN>
, are identical in all four subcells.</P>
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In our office building example, the offices are subcells of the cell <SPAN CLASS="BodyComputer">
Floor</SPAN>
. Suppose you and I both have corner offices. Mine is on the second floor and yours is above mine on the third floor. My office is 211 and your office is 311. Another way to name our offices on a building plan might be <SPAN CLASS="BodyComputer">
FloorTwo.11</SPAN>
 for my office and <SPAN CLASS="BodyComputer">
FloorThree.11</SPAN>
 for your office. This shows that <SPAN CLASS="BodyComputer">
FloorTwo.11</SPAN>
 is a subcell of <SPAN CLASS="BodyComputer">
FloorTwo</SPAN>
 and also makes it clear that, apart from being on different floors, your office and mine are identical. Both our offices have instance names <SPAN CLASS="BodyComputer">
11</SPAN>
 and are instances of cell name <SPAN CLASS="BodyComputer">
Corner</SPAN>
.</P>
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9.1.5&nbsp;Nets</H3>
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The schematics shown in <A HREF="#29121" CLASS="XRef">
Figure&nbsp;9.4</A>
 contain both <A NAME="marker=30354">
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<SPAN CLASS="Definition">
local nets</SPAN>
 and <A NAME="marker=30355">
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<SPAN CLASS="Definition">
external nets</SPAN>
. An example of a local net in <A HREF="#29121" CLASS="XRef">
Figure&nbsp;9.4</A>
(b) is <SPAN CLASS="BodyComputer">
n1</SPAN>
, the connection between the output terminal of the <SPAN CLASS="BodyComputer">
AND</SPAN>
 cell <SPAN CLASS="BodyComputer">
and1</SPAN>
 to the <SPAN CLASS="BodyComputer">
OR</SPAN>
 cell <SPAN CLASS="BodyComputer">
or1</SPAN>
. When the four copies of this circuit are placed in the parent cell <SPAN CLASS="BodyComputer">
FourBit </SPAN>
in <A HREF="#42193" CLASS="XRef">
Figure&nbsp;9.5</A>
(d), four copies of net <SPAN CLASS="BodyComputer">
n1</SPAN>
 are created. Since the four nets named <SPAN CLASS="BodyComputer">
n1</SPAN>
 are not actually electrically connected, even though they have the same name at the lowest hierarchical level, we must somehow find a way to uniquely identify each net. </P>
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The usual convention for naming nets in a hierarchical schematic uses the parent cell instance name as a prefix to the local net name. A special character (<SPAN CLASS="BodyComputer">
':' '/' '$' '#'</SPAN>
 for example) that is not allowed to appear in names is used as a <A NAME="marker=30363">
 </A>
<SPAN CLASS="Definition">
delimiter</SPAN>
 to separate the net name from the cell instance name. Supposing that we drew the subschematic for cell <SPAN CLASS="BodyComputer">
FourBit</SPAN>
 as shown in <A HREF="#42193" CLASS="XRef">
Figure&nbsp;9.5</A>
(b), the four different nets labeled <SPAN CLASS="BodyComputer">
n1</SPAN>
 might then become:</P>
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<SPAN CLASS="BodyComputer">
FourBit</SPAN>
.L1:n1  <SPAN CLASS="BodyComputer">
FourBit</SPAN>
.L2:n1  <SPAN CLASS="BodyComputer">
FourBit</SPAN>
.L3:n1  <SPAN CLASS="BodyComputer">
FourBit</SPAN>
.L4:n1</P>
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This naming is usually done automatically by the schematic-entry tool.</P>
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The schematic <SPAN CLASS="BodyComputer">
DLAT </SPAN>
also contains three external nets: <SPAN CLASS="BodyComputer">
D, EN,</SPAN>
 and <SPAN CLASS="BodyComputer">
Q</SPAN>
. The terminals on the symbol <SPAN CLASS="BodyComputer">
DLAT </SPAN>
connect these nets to other nets in the hierarchical level above. For example, the signal <SPAN CLASS="BodyComputer">
Trigger:flag</SPAN>
 in <A HREF="#29121" CLASS="XRef">
Figure&nbsp;9.4</A>
(c) is also <SPAN CLASS="BodyComputer">
Trigger.DLAT:Q</SPAN>
. Each schematic tool handles this situation differently, and life becomes especially difficult when we need to refer to these nodes from a simulator outside the schematic tool, for example. HDLs such as VHDL and Verilog have a very precise and well-defined standard for naming nets in hierarchical structures. </P>
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9.1.6&nbsp;Schematic Entry for ASICs and PCBs </H3>
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A symbol on a schematic may represent a <A NAME="marker=30438">
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component, which may contain <A NAME="marker=30439">
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component parts. You are more likely to come across the use of components in a PCB schematic. A component is slightly different from an ASIC library cell. A simple example of a component would be a TTL gate, an SN74LS00N, that contains four 2-input NAND gates. We call an SN74LS00N a <A NAME="marker=30441">
 </A>
component and each of the individual NAND gates inside is a <A NAME="marker=30442">
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component part. Another common example of a component would be a resistor pack&#8212;a single package that contains several identical resistors.</P>
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In PCB design language a component label or name is a <A NAME="marker=30443">
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<SPAN CLASS="Definition">
reference designator</SPAN>
. A reference designator is a unique name attribute, such as <SPAN CLASS="BodyComputer">
R99</SPAN>
, attached to each component. A reference designator, such as <SPAN CLASS="BodyComputer">
R99</SPAN>
, has two pieces: an alpha prefix <SPAN CLASS="BodyComputer">
R </SPAN>
and a numerical suffix <SPAN CLASS="BodyComputer">
99</SPAN>
. To understand the difference between reference designators and instance names, we need to look at the special requirements of PCB design.</P>
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PCBs usually contain packaged ASICs and other ICs that have pins that are soldered to a board. For rectangular, dual-in-line (DIP) packages the pins are numbered counterclockwise from the upper-left corner looking down on the package.</P>
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IC symbols have a <A NAME="marker=30446">
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<SPAN CLASS="Definition">
pin number</SPAN>
 for each part in the package. For example, the TTL 74174 hex D flip-flop with clear, contains six parts: six identical D flip-flops. The IC symbol representing this device has six <SPAN CLASS="BodyComputer">
PinNumber</SPAN>
 attribute entries for the D input corresponding to the six possible input pins. They are pins 3, 4, 6, 11, 13, and 14.</P>
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When we need a flip-flop in our design, we use a symbol for a 74174 from a schematic library, suppose the symbol name is <SPAN CLASS="BodyComputer">
dffClr</SPAN>
. We shall assign a unique instance name to the symbol, <SPAN CLASS="BodyComputer">
CarryFF</SPAN>