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<P>[ <A HREF="CH09.htm">Chapter start</A> ] [ <A HREF="CH09.6.htm">Previous page</A> ] [ <A HREF="CH09.8.htm">Next page</A> ]</P><!--#include file="AmazonAsic.html"--><HR></DIV>
<H1 CLASS="Heading1">
<A NAME="pgfId=4846">
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9.7 <A NAME="28803">
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Problems</H1>
<P CLASS="ExerciseHead">
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</A>
9.1 (EDIF description) </P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=32829">
</A>
a. (5 min.) Write an EDIF description for an icon for an inverter (just the input and output wires, a triangle, and a bubble). What problems do you face and what assumptions did you make? </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=32830">
</A>
b. (30 min.+) Try and import your symbol into your schematic-entry tool. If you fail (as you might) explain what the problem is and suggest a direction of attack. <SPAN CLASS="Emphasis">
Hint:</SPAN>
If you can, try Problem <A HREF="#16517" CLASS="XRef">
9.2</A>
first.</LI>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=14672">
</A>
9.2 <A NAME="16517">
</A>
(EDIF inverter, 15 min.) If you have access to a tool that generates EDIF for the icons, write out the EDIF for an inverter icon. Explain the code.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=22316">
</A>
9.3 (EDIF netlist, 20 min.) Starting with an empty directory and using a schematic editor (such as Viewlogic) draw a schematic with a single inverter (from any cell library). </P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=32831">
</A>
a. List the files that are created in the directory. </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=32832">
</A>
b. Print each one (check first to make sure it is ASCII, not binary). </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=32833">
</A>
c. Try and explain the contents.</LI>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=22322">
</A>
9.4 (Minitutorial, 60 min.) Write a minitutorial (no more than five pages) that explains how to set up your system (location and nature of any start-up files such as <SPAN CLASS="BodyComputer">
.ini</SPAN>
files for Viewlogic and so on); how to choose or change a library (for cell icons); how to choose cells, instantiate, label, and connect them; how to select, copy and delete symbols; and how to save a schematic. Use a single inverter connected to an input and output pad as an example.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=22332">
</A>
9.5 (Icons, 30 min.) With an example show how to edit and create a symbol icon. Make a triangular icon (the same size as an inverter in your library but without a bubble) for a series connection of two inverters and call it <SPAN CLASS="BodyComputer">
myBuffer</SPAN>
.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=22335">
</A>
9.6 (Buses, 30 min.) </P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=32843">
</A>
a. Create an example of a 16-bit bus: connect 8 inverters to bit zero (the MSB or leftmost bit) and bits 10–16 (as if we were taking the sign bit, bit zero, and the seven least-significant bits from a 16-bit signed number). Name the inverter connected to the sign bit, <SPAN CLASS="BodyComputer">
SIGN</SPAN>
. Name the other inverters <SPAN CLASS="BodyComputer">
BIT0</SPAN>
through <SPAN CLASS="BodyComputer">
BIT7</SPAN>
. </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=32844">
</A>
b. Write the netlist as an EDIF file, number the lines, and explain the contents by referencing line numbers.</LI>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=22339">
</A>
9.7 (VDD and VSS, 30 min.) Using a simple example of two inverters (one with input connected to VDD, the other with input connected to VSS or GND) explain how your schematic-entry system handles global power and ground nets and their connection to cell pins. Can you connect VDD or VSS to an output pin in your system? If your schematic software has a netlist screener, try it on this example.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=22340">
</A>
9.8 (Hierarchy, 30 min.) Create a very simple hierarchical cell. The lowest level, named <SPAN CLASS="BodyComputer">
bottom</SPAN>
, contains a single inverter (named <SPAN CLASS="BodyComputer">
invB</SPAN>
). The highest level, called <SPAN CLASS="BodyComputer">
top</SPAN>
, contains another inverter, <SPAN CLASS="BodyComputer">
invT</SPAN>
, whose input is connected to the output of cell <SPAN CLASS="BodyComputer">
bottom</SPAN>
. Write out the netlist (in internal and EDIF format) and explain how the tool labels a hierarchical cell.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=22345">
</A>
9.9 (Vectored instances, 30 min.) Create a vectored instance of eight inverters, <SPAN CLASS="BodyComputer">
inv0</SPAN>
through <SPAN CLASS="BodyComputer">
inv7</SPAN>
. Write the netlist in internal and EDIF form and explain the contents.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=22348">
</A>
9.10 (Dangling wires, 30 min.) Create a cell, <SPAN CLASS="BodyComputer">
dangle1</SPAN>
, containing two inverters, <SPAN CLASS="BodyComputer">
inv1</SPAN>
and <SPAN CLASS="BodyComputer">
inv2</SPAN>
. Connect the input of <SPAN CLASS="BodyComputer">
inv1</SPAN>
to an external connector, <SPAN CLASS="BodyComputer">
in1</SPAN>
, and the output of <SPAN CLASS="BodyComputer">
inv2</SPAN>
to an external connector <SPAN CLASS="BodyComputer">
out2</SPAN>
. Write the netlist and explain what happens to the unlabeled and unused nets. If you have a netlist screener, run it on this example.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=22663">
</A>
9.11 (PLD languages, 60 min.) Conduct a Web search on ABEL, CUPL, or PALASM (start by searching for “Logical Devices” not “ABEL”). Try and find examples of these files and write an explanation of their function using the descriptions of these languages in this chapter.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=28902">
</A>
9.12 (EDIF 3 0 0, 10 min.) Download the EDIF 3 0 0 example schematic file from <SPAN CLASS="URL">
<A HREF="http://www.edif.org/edif/work-shop.edf" CLASS="URL">
http://www.edif.org/edif/workshop.edf</A>
</SPAN>
and see if your EDIF reader will accept it. What is it? </P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=26714">
</A>
9.13 (EXPRESS-G, 15 min.) Draw an EXPRESS-G diagram for the government of your country. For example, in the United States you would start with the president and the White House and work down through the House and Senate, showing the senators and congressional representatives. In the United Kingdom you would draw the prime minister, the House of Commons, and House of Lords with the various MPs.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=27261">
</A>
9.14 (ABEL PCI Target) (10 min.) Download the Xilinx Application Note, Designing Flexible PCI Interfaces with Xilinx EPLDs, January 1995 (<SPAN CLASS="BodyComputer">
pci_epld.pdf</SPAN>
at <SPAN CLASS="BodyComputer">
www.xilinx.com</SPAN>
). The Appendix of this App. Note contains the ABEL source code for a PCI Bus Interface Target. The code is long but straightforward; most of it describes the next-state transitions for the bus-controller state machine. Extract the ABEL source code using Adobe Acrobat. <SPAN CLASS="Emphasis">
Hint:</SPAN>
This is not easy; Acrobat does a poor job of selecting text; you will lose many semicolons at the end of lines that you will have to add by hand. Use Replace... to search for end-of-line, <SPAN CLASS="BodyComputer">
"^p"</SPAN>
, and replace by <SPAN CLASS="BodyComputer">
" ; ^p"</SPAN>
in Word. (60 min.+) Try to convert this code to a system where you can compile it. You may need conversion utilities to do this. For example Altera (<SPAN CLASS="BodyComputer">
www.altera.com</SPAN>
) has utilities (<SPAN CLASS="BodyComputer">
EAU018.EXE</SPAN>
and <SPAN CLASS="BodyComputer">
EAU019.EXE</SPAN>
located at <SPAN CLASS="URL">
<A HREF="ftp://ftp.altera.com/pub" CLASS="URL">
ftp.altera.com/pub</A>
</SPAN>
) to convert from ABEL 4.0 to AHDL.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=27406">
</A>
9.15 (CUPL, 60 min.) Download and install the CUPL demonstration package from <SPAN CLASS="URL">
<A HREF="http://www.protel.com/download.htm" CLASS="URL">
http://www.protel.com/download.htm</A>
</SPAN>
<SPAN CLASS="BodyComputer">
</SPAN>
. Write a two-page help sheet on what you did, where the software is installed, and how to run it.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=26784">
</A>
9.16 (PALASM) (30 min.) Download and install PALASM4 v1.5 from the AMD Web site at <SPAN CLASS="URL">
<A HREF="ftp://ftp.amd.com/pub/pld/software/palasm" CLASS="URL">
ftp://ftp.amd.com/pub/pld/software/palasm</A>
</SPAN>
. </P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=28724">
</A>
9.17 (CUPL) </P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=32861">
</A>
a. (15 min.) Check the equations in the CUPL code for the 4-bit counter in <A HREF="CH09.2.htm#10372" CLASS="XRef">
Section 9.2</A>
. </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=32862">
</A>
b. (10 min.) Add a count-enable signal to the code. </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=33883">
</A>
c. (30 min.) If you have access to CUPL, compile your answer.</LI>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=31162">
</A>
9.18 (EDIF) </P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=32863">
</A>
a. (30 min.) Using the syntax definitions below and the example schematic icon shown in <A HREF="CH09.4.htm#24981" CLASS="XRef">
Table 9.12</A>
to help you, “stitch” back together the EDIF definition for the 7404 inverter symbol used as an example in <A HREF="CH09.4.htm#38118" CLASS="XRef">
Section 9.4.3</A>
. </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=32864">
</A>
b. (60 min.+) Try to import the EDIF into your schematic entry system. Comment on any problems and how you attempted to resolve them (including failures).</LI>
</UL>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=31166">
</A>
The <A NAME="marker=31165">
</A>
<SPAN CLASS="Definition">
EDIF Reference Manual</SPAN>
[<A NAME="EDIF, 1988">
</A>
EDIF, 1988] uses the following metasyntax rules:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=31167">
</A>
[optional] <at most once> {may be repeated zero or more times}</P>
<P CLASS="Computer">
<A NAME="pgfId=31168">
</A>
{this|that} indicates any number of this or that in any order</P>
<P CLASS="Computer">
<A NAME="pgfId=31169">
</A>
syntactic names are italic</P>
<P CLASS="Computer">
<A NAME="pgfId=31170">
</A>
literal words are bold</P>
<P CLASS="Computer">
<A NAME="pgfId=31171">
</A>
SYMBOLIC constants are uppercase</P>
<P CLASS="Computer">
<A NAME="pgfId=31172">
</A>
IdentifierNameDef means the name is being defined</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=31173">
</A>
IdentifierNameRef means the name is being referenced</P>
<P CLASS="Body">
<A NAME="pgfId=31174">
</A>
The syntax definitions of the most common EDIF constructs for schematics are as follows:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=31175">
</A>
(edif edifFileNameDef</P>
<P CLASS="Computer">
<A NAME="pgfId=31176">
</A>
edifVersion</P>
<P CLASS="Computer">
<A NAME="pgfId=31177">
</A>
edifLevel</P>
<P CLASS="Computer">
<A NAME="pgfId=31178">
</A>
keywordMap</P>
<P CLASS="Computer">
<A NAME="pgfId=31179">
</A>
{<status>|external|library|design|comment|userdata} )</P>
<P CLASS="Computer">
<A NAME="pgfId=31181">
</A>
(library libraryNameDef</P>
<P CLASS="Computer">
<A NAME="pgfId=31182">
</A>
edifLevel</P>
<P CLASS="Computer">
<A NAME="pgfId=31183">
</A>
technology</P>
<P CLASS="Computer">
<A NAME="pgfId=31184">
</A>
{<status>|cell|comment|userdata} )</P>
<P CLASS="Computer">
<A NAME="pgfId=31186">
</A>
(technology numberDefinition</P>
<P CLASS="Computer">
<A NAME="pgfId=31187">
</A>
{figureGroup|fabricate|</P>
<P CLASS="Computer">
<A NAME="pgfId=31188">
</A>
<simulationInfos>|<physicalDesignRule>|comment|userdata} )</P>
<P CLASS="Computer">
<A NAME="pgfId=31190">
</A>
(cell cellNameDef</P>
<P CLASS="Computer">
<A NAME="pgfId=31191">
</A>
cellType</P>
<P CLASS="Computer">
<A NAME="pgfId=31192">
</A>
{<status>|view|<viewMap>|property|comment|userdata} )</P>
<P CLASS="Computer">
<A NAME="pgfId=31194">
</A>
(view viewNameDef</P>
<P CLASS="Computer">
<A NAME="pgfId=31195">
</A>
viewType</P>
<P CLASS="Computer">
<A NAME="pgfId=31196">
</A>
interface</P>
<P CLASS="Computer">
<A NAME="pgfId=31197">
</A>
{<status>|<contents>|comment|property|userdata} )</P>
<P CLASS="Computer">
<A NAME="pgfId=31199">
</A>
(interface</P>
<P CLASS="Computer">
<A NAME="pgfId=31200">
</A>
{port|portBundle|<symbol>|<protectionFrame>|</P>
<P CLASS="Computer">
<A NAME="pgfId=31201">
</A>
<arrayRelatedInfo>|parameter|joined|mustJoin|weakJoined|</P>
<P CLASS="Computer">
<A NAME="pgfId=31202">
</A>
permutable|timing|simulate|<designator>|property|comment|userdata} )</P>
<P CLASS="Computer">
<A NAME="pgfId=31204">
</A>
(contents</P>
<P CLASS="Computer">
<A NAME="pgfId=31205">
</A>
{instance|offPageConnector|figure|section|</P>
<P CLASS="Computer">
<A NAME="pgfId=31206">
</A>
net|netBundle|page|commentGraphics|portImplementation|</P>
<P CLASS="Computer">
<A NAME="pgfId=31207">
</A>
timing|simulate|when|follow|logicPort|<boundingBox>|</P>
<P CLASS="Computer">
<A NAME="pgfId=31208">
</A>
comment|userdata} )</P>
<P CLASS="Computer">
<A NAME="pgfId=31210">
</A>
(viewMap</P>
<P CLASS="Computer">
<A NAME="pgfId=31211">
</A>
{portMap|portBackAnnotate|instanceMap|instanceBackAnnotate|</P>
<P CLASS="Computer">
<A NAME="pgfId=31212">
</A>
netMap|netBackAnnotate|comment|userdata} )</P>
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