ch09.2.htm

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<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27749">

 </A>

T input to a T register</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27751">

 </A>

&nbsp;</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27753">

 </A>

IO</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27755">

 </A>

R</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27757">

 </A>

Pin feedback of registered output</P>

</TD>

</TR>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27759">

 </A>

DQ</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27761">

 </A>

R</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27763">

 </A>

D output of an input D register</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27765">

 </A>

&nbsp;</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27767">

 </A>

IOD/T</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27769">

 </A>

R</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27771">

 </A>

D/T register on pin feedback path selection</P>

</TD>

</TR>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27773">

 </A>

LQ</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27775">

 </A>

R</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27777">

 </A>

Q output of an input latch</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27779">

 </A>

&nbsp;</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27781">

 </A>

IOL</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27783">

 </A>

R</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27785">

 </A>

Latch on pin feedback path </P>

<P CLASS="TableLeft">

<A NAME="pgfId=27786">

 </A>

selection</P>

</TD>

</TR>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27788">

 </A>

AP, AR</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27790">

 </A>

L</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27792">

 </A>

Asynchronous preset/reset</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27794">

 </A>

&nbsp;</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27796">

 </A>

IOAP, IOAR</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27798">

 </A>

L</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27800">

 </A>

Asynchronous preset/reset of </P>

<P CLASS="TableLeft">

<A NAME="pgfId=27801">

 </A>

register on feedback path</P>

</TD>

</TR>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27803">

 </A>

SP, SR</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27805">

 </A>

L</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27807">

 </A>

Synchronous preset/reset</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27809">

 </A>

&nbsp;</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27811">

 </A>

IOSP, IOSR</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27813">

 </A>

L</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27815">

 </A>

Synchronous preset/reset of</P>

<P CLASS="TableLeft">

<A NAME="pgfId=27816">

 </A>

register on feedback path</P>

</TD>

</TR>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27818">

 </A>

CK</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27820">

 </A>

L</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27822">

 </A>

Product clock term (async.)</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27824">

 </A>

&nbsp;</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27826">

 </A>

IOCK</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27828">

 </A>

L</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27830">

 </A>

Clock for pin feedback register</P>

</TD>

</TR>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27832">

 </A>

OE</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27834">

 </A>

L</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27836">

 </A>

Product-term output enable</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27838">

 </A>

&nbsp;</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27840">

 </A>

APMUX, ARMUX</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27842">

 </A>

L</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27844">

 </A>

Asynchronous preset/reset </P>

<P CLASS="TableLeft">

<A NAME="pgfId=27845">

 </A>

multiplexor selection</P>

</TD>

</TR>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27847">

 </A>

CA</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27849">

 </A>

L</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27851">

 </A>

Complement array</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27853">

 </A>

&nbsp;</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27855">

 </A>

CKMUX</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27857">

 </A>

L</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27859">

 </A>

Clock multiplexor selector</P>

</TD>

</TR>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27861">

 </A>

PR</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27863">

 </A>

L</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27865">

 </A>

Programmable preload</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27867">

 </A>

&nbsp;</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27869">

 </A>

LEMUX</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27871">

 </A>

L</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27873">

 </A>

Latch enable multiplexor selector</P>

</TD>

</TR>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27875">

 </A>

CE</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27877">

 </A>

L</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27879">

 </A>

CE input of a D-CE register</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27881">

 </A>

&nbsp;</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27883">

 </A>

OEMUX</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27885">

 </A>

L</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27887">

 </A>

Output enable multiplexor </P>

<P CLASS="TableLeft">

<A NAME="pgfId=27888">

 </A>

selector</P>

</TD>

</TR>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27890">

 </A>

LE</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27892">

 </A>

L</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27894">

 </A>

Product-term latch enable</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27896">

 </A>

&nbsp;</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27898">

 </A>

IMUX</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27900">

 </A>

L</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27902">

 </A>

Input multiplexor selector of</P>

<P CLASS="TableLeft">

<A NAME="pgfId=27903">

 </A>

two pins</P>

</TD>

</TR>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27905">

 </A>

OBS</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27907">

 </A>

L</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27909">

 </A>

Programmable observability of buried nodes</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27911">

 </A>

&nbsp;</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27913">

 </A>

TEC</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27915">

 </A>

L</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27917">

 </A>

Technology-dependent fuse selection</P>

</TD>

</TR>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27919">

 </A>

BYP</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27921">

 </A>

L</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27923">

 </A>

Programmable register bypass</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27925">

 </A>

&nbsp;</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27927">

 </A>

T1</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27929">

 </A>

L</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27931">

 </A>

T1 input of 2-T register</P>

</TD>

</TR>

</TABLE>

<P CLASS="Body">

<A NAME="pgfId=30756">

 </A>

The 4-bit counter is a very simple example of the use of the Atmel ATV2500B. This PLD is quite complex and has many extra &#8220;buried&#8221; features. In order to use these features in CUPL (and ABEL) you need to refer to special pin numbers and node numbers that are given in tables in the manufacturer&#8217;s data sheets. You may need the pin-number tables to reverse engineer or convert a complicated CUPL (or ABEL) design from one format to another. </P>

<P CLASS="Body">

<A NAME="pgfId=30798">

 </A>

Atmel also gives skeleton headers and pin declarations for their parts in their data sheets. <A HREF="#37237" CLASS="XRef">

Table&nbsp;9.6</A>

 shows the headers and pin declarations in ABEL and CUPL format for the ATMEL ATV2500B. </P>

<TABLE>

<TR>

<TH ROWSPAN="1" COLSPAN="2">

<P CLASS="TableTitle">

<A NAME="pgfId=30763">

 </A>

TABLE&nbsp;9.6&nbsp;<A NAME="37237">

 </A>

ABEL and CUPL pin declarations for an ATMEL ATV2500B.</P>

</TH>

</TR>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableFirst">

<A NAME="pgfId=30767">

 </A>

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