ch09.2.htm

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<SPAN CLASS="BodyComputer">

A = B $ C;</SPAN>

</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33782">

 </A>

Logical exclusive-OR</P>

</TD>

</TR>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33784">

 </A>

Comment</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33786">

 </A>

<SPAN CLASS="BodyComputer">

A = B &amp; C /* comment */</SPAN>

</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33788">

 </A>

&nbsp;</P>

</TD>

</TR>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33790">

 </A>

Pin declaration</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33792">

 </A>

<SPAN CLASS="BodyComputer">

PIN 1 = CLK;</SPAN>

</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33794">

 </A>

Device dependent</P>

</TD>

</TR>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33796">

 </A>

&nbsp;</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33798">

 </A>

<SPAN CLASS="BodyComputer">

PIN = CLK; </SPAN>

</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33800">

 </A>

Device independent</P>

</TD>

</TR>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33802">

 </A>

Node declaration</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33804">

 </A>

<SPAN CLASS="BodyComputer">

NODE A;</SPAN>

</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33806">

 </A>

Number automatically assigned</P>

</TD>

</TR>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33808">

 </A>

&nbsp;</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33810">

 </A>

<SPAN CLASS="BodyComputer">

NODE [B0..7];</SPAN>

</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33812">

 </A>

Array of buried nodes</P>

</TD>

</TR>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33814">

 </A>

Pinnode declaration</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33816">

 </A>

<SPAN CLASS="BodyComputer">

PINNODE 99 = A;</SPAN>

</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33818">

 </A>

Node assigned by designer</P>

</TD>

</TR>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33820">

 </A>

&nbsp;</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33822">

 </A>

<SPAN CLASS="BodyComputer">

PINNODE [10..17] = [B0..7];</SPAN>

</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33824">

 </A>

Array of pinnodes</P>

</TD>

</TR>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33826">

 </A>

Bit-field declaration</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33828">

 </A>

<SPAN CLASS="BodyComputer">

FIELD Address = [B0..7];</SPAN>

</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33830">

 </A>

8-bit address field</P>

</TD>

</TR>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33832">

 </A>

Bit-field operations</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33834">

 </A>

<SPAN CLASS="BodyComputer">

add_one = Address:FF;</SPAN>

</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33836">

 </A>

True if Address = OxFF</P>

</TD>

</TR>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33838">

 </A>

&nbsp;</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33840">

 </A>

<SPAN CLASS="BodyComputer">

add_zero = !(Address:&amp;);</SPAN>

</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33842">

 </A>

True if Address = Ox00</P>

</TD>

</TR>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33844">

 </A>

&nbsp;</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33846">

 </A>

<SPAN CLASS="BodyComputer">

add_range = Address:[0F..FF];</SPAN>

</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=33848">

 </A>

True if 0F.LE.Address.LE.FF </P>

</TD>

</TR>

</TABLE>

<P CLASS="Body">

<A NAME="pgfId=27995">

 </A>

The extensions steer the software, known as a <SPAN CLASS="Definition">

fitter</SPAN>

<A NAME="marker=30733">

 </A>

, in assigning the logic. For example, a signal-name suffix of <SPAN CLASS="BodyComputer">

.OE</SPAN>

 marks that signal as an output enable. </P>

<P CLASS="Body">

<A NAME="pgfId=30749">

 </A>

Here is an example of a CUPL file for a 4-bit counter placed in an ATMEL PLD part that illustrates the use of some common extensions:</P>

<P CLASS="ComputerFirst">

<A NAME="pgfId=27940">

 </A>

Name 4BIT; Device V2500B;</P>

<P CLASS="Computer">

<A NAME="pgfId=27955">

 </A>

/* inputs */</P>

<P CLASS="Computer">

<A NAME="pgfId=27957">

 </A>

pin 1 = CLK; pin 3 = LD_; pin 17 = RST_; </P>

<P CLASS="Computer">

<A NAME="pgfId=28329">

 </A>

pin [18,19,20,21] = [I0,I1,I2,I3];</P>

<P CLASS="Computer">

<A NAME="pgfId=27963">

 </A>

/*  outputs  */</P>

<P CLASS="Computer">

<A NAME="pgfId=27965">

 </A>

pin [4,5,6,7] = [Q0,Q1,Q2,Q3]; </P>

<P CLASS="Computer">

<A NAME="pgfId=27971">

 </A>

field CNT = [Q3,Q2,Q1,Q0];</P>

<P CLASS="Computer">

<A NAME="pgfId=28355">

 </A>

/* equations */</P>

<P CLASS="Computer">

<A NAME="pgfId=27973">

 </A>

Q3.T = (!Q2 &amp; !Q1 &amp; !Q0) &amp; LD_ &amp; RST_ /* count down */</P>

<P CLASS="Computer">

<A NAME="pgfId=27974">

 </A>

     # Q3 &amp; !RST_ /* ReSeT */</P>

<P CLASS="Computer">

<A NAME="pgfId=27975">

 </A>

     # (Q3 $ I3) &amp; !LD_; /* LoaD*/</P>

<P CLASS="Computer">

<A NAME="pgfId=27977">

 </A>

Q2.T = (!Q1 &amp; !Q0) &amp; LD_ &amp; RST_ # Q2 &amp; !RST_ # (Q2 $ I2) &amp; !LD_;</P>

<P CLASS="Computer">

<A NAME="pgfId=28312">

 </A>

Q1.T = !Q0 &amp; LD_ &amp; RST_ # Q1 &amp; !RST_ # (Q1 $ I1) &amp; !LD_; </P>

<P CLASS="Computer">

<A NAME="pgfId=28313">

 </A>

Q0.T = LD_ &amp; RST_ # Q0 &amp; !RST_ # (Q0 $ I0) &amp; !LD_; </P>

<P CLASS="ComputerLast">

<A NAME="pgfId=28314">

 </A>

CNT.CK = CLK; CNT.OE = 'h'F; CNT.AR = 'h'0; CNT.SP = 'h'0;</P>

<P CLASS="Body">

<A NAME="pgfId=27936">

 </A>

In this example the suffix extensions have the following effects: <SPAN CLASS="BodyComputer">

.CK</SPAN>

 marks the clock; <SPAN CLASS="BodyComputer">

.T</SPAN>

 configures sequential logic as T flip-flops; <SPAN CLASS="BodyComputer">

.OE</SPAN>

 (wired high) is the output enable; <SPAN CLASS="BodyComputer">

.AR</SPAN>

 (wired low) is the asynchronous reset; and <SPAN CLASS="BodyComputer">

.SP</SPAN>

 (wired low) is the synchronous preset. <A HREF="#20869" CLASS="XRef">

Table&nbsp;9.5</A>

 shows the different CUPL extensions. </P>

<TABLE>

<TR>

<TD ROWSPAN="1" COLSPAN="7">

<P CLASS="TableTitle">

<A NAME="pgfId=27655">

 </A>

TABLE&nbsp;9.5&nbsp;<A NAME="20869">

 </A>

CUPL 4.0 extensions.</P>

</TD>

</TR>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableFirst">

<A NAME="pgfId=27672">

 </A>

<SPAN CLASS="TableHeads">

Extension<A HREF="#pgfId=27671" CLASS="footnote">

1</A>

</SPAN>

</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableFirst">

<A NAME="pgfId=27674">

 </A>

&nbsp;</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableFirst">

<A NAME="pgfId=27676">

 </A>

<SPAN CLASS="TableHeads">

	Explanation</SPAN>

</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableFirst">

<A NAME="pgfId=27678">

 </A>

&nbsp;</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableFirst">

<A NAME="pgfId=27680">

 </A>

<SPAN CLASS="TableHeads">

Extension</SPAN>

</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableFirst">

<A NAME="pgfId=27682">

 </A>

&nbsp;</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableFirst">

<A NAME="pgfId=27684">

 </A>

<SPAN CLASS="TableHeads">

Explanation</SPAN>

</P>

</TD>

</TR>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27686">

 </A>

D</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27688">

 </A>

L</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27690">

 </A>

D input to a D register</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27692">

 </A>

&nbsp;</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27694">

 </A>

DFB</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27696">

 </A>

R</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27698">

 </A>

D register feedback of </P>

<P CLASS="TableLeft">

<A NAME="pgfId=27699">

 </A>

combinational output</P>

</TD>

</TR>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27701">

 </A>

L</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27703">

 </A>

L</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27705">

 </A>

L input to a latch</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27707">

 </A>

&nbsp;</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27709">

 </A>

LFB</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27711">

 </A>

R</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27713">

 </A>

Latched feedback of </P>

<P CLASS="TableLeft">

<A NAME="pgfId=27714">

 </A>

combinational output</P>

</TD>

</TR>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27716">

 </A>

J, K</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27718">

 </A>

L</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27720">

 </A>

J-K-input to a J-K register</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27722">

 </A>

&nbsp;</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27724">

 </A>

TFB</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27726">

 </A>

R</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27728">

 </A>

T register feedback of</P>

<P CLASS="TableLeft">

<A NAME="pgfId=27729">

 </A>

combinational output</P>

</TD>

</TR>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27731">

 </A>

S, R</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27733">

 </A>

L</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27735">

 </A>

S-R input to an S-R register</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27737">

 </A>

&nbsp;</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27739">

 </A>

INT</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27741">

 </A>

R</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27743">

 </A>

Internal feedback</P>

</TD>

</TR>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27745">

 </A>

T</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableLeft">

<A NAME="pgfId=27747">

 </A>

L</P>

</TD>
12345

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