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-- defined for types, T and F, where 
-- F=BIT BIT_VECTOR STD_ULOGIC STD_ULOGIC_VECTOR STD_LOGIC_VECTOR
-- T=types F plus types X01 X01Z UX01 (but not type UX01Z)
-- Exclude _'s in T in name: TO_STDULOGIC not TO_STD_ULOGIC
-- To_XO1 : L->0, H->1 others->X
-- To_XO1Z: Z->Z, others as To_X01
-- To_UX01: U->U, others as To_X01
-- Edge detection functions:
<B>function</B> rising_edge&nbsp;&nbsp;(<B>signal</B> s: STD_ULOGIC) <B>return</B> BOOLEAN;
<B>function</B> falling_edge (<B>signal</B> s: STD_ULOGIC) <B>return</B> BOOLEAN;
-- Unknown detection (returns true if s = U, X, Z, W):
-- function Is_X (s : T) return BOOLEAN;
-- defined for T = STD_ULOGIC STD_ULOGIC_VECTOR STD_LOGIC_VECTOR.
<B>end</B> Part_STD_LOGIC_1164;</PRE>

<P><P CLASS="Body"><A NAME="pgfId=20944"></A>Notice:</P>

<UL>
  <LI><A NAME="pgfId=20945"></A>The type <CODE>STD_ULOGIC</CODE> has nine
  logic values. For this reason IEEE Std 1164 is sometimes referred to as
  MVL9--multivalued logic nine. There are simpler, but nonstandard, MVL4
  and MVL7 packages, as well as packages with more than nine logic values,
  available. Values <CODE>'U'</CODE> , <CODE>'X'</CODE> , and <CODE>'W'</CODE>
  are all metalogical values.
  <LI><A NAME="pgfId=88487"></A>There are weak and forcing logic-value strengths.
  If more than one logic gate drives a node (there is more than one driver)
  as in wired-OR logic or a three-state bus, for example, the simulator checks
  the driver strengths to resolve the actual logic value of the node using
  the resolution function, <CODE>resolved</CODE> , defined in the package.
  <LI><A NAME="pgfId=20946"></A>The subtype <CODE>STD_LOGIC</CODE> is the
  resolved version of the unresolved type <CODE>STD_ULOGIC</CODE>. Since
  subtypes are compatible with types (you can assign one to the other) you
  can use either <CODE>STD_LOGIC</CODE> or <CODE>STD_ULOGIC</CODE> for a
  signal with a single driver, but it is generally safer to use <CODE>STD_LOGIC</CODE>.
  <LI><A NAME="pgfId=65247"></A>The type <CODE>STD_LOGIC_VECTOR</CODE> is
  the resolved version of unresolved type <CODE>STD_ULOGIC_VECTOR</CODE>.
  Since these are two different types and are not compatible, you should
  use <CODE>STD_LOGIC_VECTOR</CODE>. That way you will not run into a problem
  when you try to connect a <CODE>STD_LOGIC_VECTOR</CODE> to a <CODE>STD_ULOGIC_VECTOR</CODE>.
  <LI><A NAME="pgfId=20955"></A>The don't care logic value <CODE>'-'</CODE>
  (hyphen), is principally for use by synthesis tools. The value <CODE>'-'</CODE>
  is almost always treated the same as <CODE>'X'</CODE>.
  <LI><A NAME="pgfId=238656"></A>The 1164 standard defines (or overloads)
  the logical operators for the <CODE>STD_LOGIC</CODE> types but not the
  arithmetic operators (see Section&nbsp;10.12).
</UL>

<H3><A NAME="pgfId=238659"></A>10.6.3&nbsp; Textio Package</H3>

<P><P CLASS="BodyAfterHead"><A NAME="pgfId=5573"></A>You can use the <B>textio</B>
package, which is part of the library <CODE>STD</CODE> , for text input
and output [<A HREF="../../VHDL/LRM/HTML/1076_14.HTM#14.3">VHDL LRM14.3</A>]. The
following code is a part of the <CODE>TEXTIO</CODE> package header and,
together with the comments, shows the declarations of types, subtypes, and
the use of the procedures in the package:</P>

<PRE><B>package</B> Part_TEXTIO <B>is </B>-- VHDL-93 version.
<B>type</B> LINE <B>is</B> <B>access</B> STRING; -- LINE is a pointer to a STRING value.
<B>type</B> TEXT <B>is</B> <B>file</B> <B>of</B> STRING; -- File of ASCII records. 
<B>type</B> SIDE <B>is</B> (RIGHT, LEFT); -- for justifying output data. 
<B>subtype</B> WIDTH <B>is</B> NATURAL; -- for specifying widths of output fields. 
<B>file</B> INPUT : TEXT <B>open</B> READ_MODE <B>is</B> &quot;STD_INPUT&quot;; -- Default input file.
<B>file</B> OUTPUT : TEXT <B>open</B> WRITE_MODE <B>is</B> &quot;STD_OUTPUT&quot;; -- Default output.
-- The following procedures are defined for types, T, where 
-- T = BIT BIT_VECTOR BOOLEAN CHARACTER INTEGER REAL TIME STRING
-- 		procedure READLINE(file F : TEXT; L : out LINE);
-- 		procedure READ(L : inout LINE; VALUE : out T);
-- 		procedure READ(L : inout LINE; VALUE : out T; GOOD: out BOOLEAN);
-- 		procedure WRITELINE(F : out TEXT; L : inout LINE);
-- 		procedure WRITE(
--			L : inout LINE; 
--			VALUE : in T; 
--			JUSTIFIED : in SIDE:= RIGHT; 
--			FIELD:in WIDTH := 0; 
--			DIGITS:in NATURAL := 0; -- for T = REAL only
--			UNIT:in TIME:= ns); -- for T = TIME only
-- function ENDFILE(F : in TEXT) return BOOLEAN;
<B>end</B> Part_TEXTIO;</PRE>

<P><P CLASS="Body"><A NAME="pgfId=238912"></A>Here is an example that illustrates
how to write to the screen (<CODE>STD_OUTPUT</CODE> ):</P>

<PRE><B>library</B> std; <B>use</B> std.textio.<B>all</B>; <B>entity</B> Text <B>is</B> <B>end</B>;
<B>architecture</B> Behave <B>of</B> Text <B>is signal</B> count : INTEGER := 0;
<B>begin</B> count &lt;= 1 <B>after</B> 10 ns, 2 <B>after</B> 20 ns, 3 <B>after</B> 30 ns;
<B>process</B> (count) <B>variable</B> L: LINE; <B>begin</B> 
<B>if</B> (count &gt; 0) <B>then</B> 
	write(L, now); -- Write time.
	write(L, STRING'(&quot; count=&quot;)); -- STRING' is a type qualification.
	write(L, count); writeline(output, L);
<B>end</B> <B>if</B>; <B>end</B> <B>process</B>; <B>end</B>;
10 ns count=1
20 ns count=2
30 ns count=3</PRE>

<H3><A NAME="pgfId=99708"></A>10.6.4&nbsp; Other Packages</H3>

<P><P CLASS="BodyAfterHead"><A NAME="pgfId=99720"></A>VHDL does not predefine
arithmetic operators on types that hold bits. Many VHDL simulators provide
one or more arithmetic packages that allow you to perform arithmetic operations
on <CODE>std_logic_1164</CODE> types. Some companies also provide one or
more math packages that contain functions for floating-point algebra, trigonometry,
complex algebra, queueing, and statistics (see also [IEEE 1076.2, 1996]).</P>

<P><P CLASS="Body"><A NAME="pgfId=99719"></A>Synthesis tool companies often
provide a special version of an arithmetic package, a synthesis package,
that allows you to synthesize VHDL that includes arithmetic operators. This
type of package may contain special instructions (normally comments that
are recognized by the synthesis software) that map common functions (adders,
subtracters, multipliers, shift registers, counters, and so on) to ASIC
library cells. I shall introduce the IEEE synthesis package in Section&nbsp;10.12.</P>

<P><P CLASS="Body"><A NAME="pgfId=256170"></A>Synthesis companies may also
provide component packages for such cells as power and ground pads, I/O
buffers, clock drivers, three-state pads, and bus keepers. These components
may be technology-independent (generic) and are mapped to primitives from
technology-dependent libraries after synthesis.</P>

<H3><A NAME="pgfId=99713"></A>10.6.5&nbsp; Creating Packages</H3>

<P><P CLASS="BodyAfterHead"><A NAME="pgfId=1384"></A>It is often useful
to define constants in one central place rather than using literals wherever
you need a specific value in your code. One way to do this is by using VHDL
packaged constants [<A HREF="../../VHDL/LRM/HTML/1076_4.HTM#4.3.1.1">VHDL LRM4.3.1.1</A>]
that you define in a package. Packages that you define are initially part
of the working library, <CODE>work</CODE> . Here are two example packages
[<A HREF="../../VHDL/LRM/HTML/1076_2.HTM#2.5">VHDL LRM2.5</A>-<A HREF="../../VHDL/LRM/HTML/1076_2.HTM#2.7">2.7</A>]:</P>

<PRE><B>package</B> Adder_Pkg <B>is</B> -- a package declaration
	<B>constant</B> BUSWIDTH : INTEGER := 16; 
<B>end</B> Adder_Pkg;
<B>use</B> work.Adder_Pkg.<B>all</B>; -- a use clause
<B>entity</B> Adder <B>is</B> <B>end</B> Adder;
<B>architecture</B> Flexible <B>of</B> Adder <B>is</B> -- work.Adder_Pkg is visible here
	<B>begin process</B> <B>begin</B> 
		MyLoop : <B>for</B> j <B>in</B> 0 to BUSWIDTH loop -- adder code goes here
		<B>end</B> <B>loop</B>; <B>wait</B>; -- the wait prevents an endless cycle
	<B>end</B> <B>process</B>;
<B>end</B> Flexible;
<B>package</B> GLOBALS <B>is</B> 
	<B>constant</B> HI : BIT := '1'; <B>constant</B> LO: BIT := '0';
<B>end</B> GLOBALS;</PRE>

<P><P CLASS="Body"><A NAME="pgfId=20986"></A>Here is a package that declares
a function and thus requires a package body:</P>

<PRE><B>package</B> Add_Pkg_Fn <B>is</B>
function add(a, b, c : BIT_VECTOR(3 downto 0)) <B>return</B> BIT_VECTOR;
<B>end</B> Add_Pkg_Fn;
<B>package body</B> Add_Pkg_Fn <B>is</B>
<B>function </B>add(a, b, c : BIT_VECTOR(3 <B>downto</B> 0)) <B>return</B> BIT_VECTOR <B>is</B>
	<B>begin</B> <B>return</B> a <B>xor</B> b <B>xor</B> c; <B>end</B>; 
<B>end</B> Add_Pkg_Fn;</PRE>

<P><P CLASS="Body"><A NAME="pgfId=256774"></A>The following example is similar
to the VITAL (VHDL Initiative Toward ASIC Libraries) package that provides
two alternative methods (procedures or functions) to model primitive gates
(I shall describe functions and procedures in more detail in Section&nbsp;10.9.2):</P>

<PRE><B>package</B> And_Pkg <B>is </B>
<B>	procedure</B> V_And(a, b : BIT; <B>signal</B> c : <B>out</B> BIT); 
<B>	function</B> V_And(a, b : BIT) <B>return</B> BIT;
<B>end</B>;
<B>package body</B> And_Pkg <B>is </B>
<B>	procedure</B> V_And(a, b : BIT; <B>signal</B> c : <B>out</B> BIT) <B>is </B>
<B>		begin</B> c &lt;= a <B>and </B>b; <B>end</B>;
<B>	function</B> V_And(a, b : BIT) <B>return</B> BIT <B>is </B>
<B>		begin</B> <B>return</B> a <B>and </B>b; <B>end</B>;
<B>end</B> And_Pkg;</PRE>

<P><P CLASS="Body"><A NAME="pgfId=113144"></A>The software determines where
it stores the design units that we analyze. Suppose the package <CODE>Add_Pkg_Fn</CODE>
is in library <CODE>MyLib</CODE> . Then we need a library clause (before
each design unit) and use clause with a selected name to use the package:</P>

<PRE><B>library</B> MyLib; -- use MyLib.Add_Pkg.all; -- use all the package
<B>use</B> MyLib.Add_Pkg_Fn.add; -- just function 'add' from the package
<B>entity</B> Lib_1 <B>is</B> <B>port</B> (s : <B>out</B> BIT_VECTOR(3 <B>downto</B> 0) := &quot;0000&quot;); <B>end</B>;
<B>architecture</B> Behave <B>of</B> Lib_1 <B>is begin</B> <B>process</B>
<B>begin</B> s &lt;= add (&quot;0001&quot;, &quot;0010&quot;, &quot;1000&quot;); <B>wait</B>; <B>end</B> <B>process</B>; <B>end</B>;</PRE>

<P><P CLASS="Body"><A NAME="pgfId=191065"></A>The VHDL software dictates
how you create the library <CODE>MyLib</CODE> from the library <CODE>work</CODE>
and the actual name and directory location for the physical file or directory
on the disk that holds the library. The mechanism to create the links between
the file and directory names in the computer world and the library names
in the VHDL world depends on the software. There are three common methods:</P>

<UL>
  <LI><A NAME="pgfId=255594"></A>Use a UNIX environment variable (<CODE>SETENV
  MyLib ~/MyDirectory/<BR>
  MyLibFile</CODE> , for example).
  <LI><A NAME="pgfId=255597"></A>Create a separate file that establishes
  the links between the filename known to the operating system and the library
  name known to the VHDL software.
  <LI><A NAME="pgfId=255598"></A>Include the links in an initialization file
  (often with an <CODE>'.ini'</CODE> suffix).
</UL>

<P><HR ALIGN="LEFT"><P CLASS="Footnote2"><SPAN CLASS="footnoteNumber"> 1.</SPAN>
<A NAME="pgfId=539243"></A>The code in this section is adapted with permission
from IEEE Std 1164-1993, &copy; Copyright IEEE. All rights reserved.</P>

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