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<H2>10.6 Packages and Libraries</H2>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=99691"></A>After the VHDL tool
has analyzed entities, architectures, and configurations, it stores the
resulting design units in a library. Much of the power of VHDL comes from
the use of predefined libraries and packages. A VHDL design library [<A HREF="../../VHDL/LRM/HTML/1076_11.HTM#11.2">VHDL LRM11.2</A>] is either the current
working library (things we are currently analyzing) or a predefined resource
library (something we did yesterday, or we bought, or that came with the
tool). The working library is named <CODE>work</CODE> and is the place where
the code currently being analyzed is stored. Architectures must be in the
same library (but they do not have to be in the same physical file on disk)
as their parent entities.</P>
<P><P CLASS="Body"><A NAME="pgfId=11711"></A>You can use a VHDL package
[<A HREF="../../VHDL/LRM/HTML/1076_2.HTM#2.5">VHDL LRM2.5</A>-<A HREF="../../VHDL/LRM/HTML/1076_2.HTM#2.6">2.6</A>]
to define subprograms (procedures and functions), declare special types,
modify the behavior of operators, or to hide complex code. Here is the BNF
for a package declaration:</P>
<PRE>package_declaration ::=
<B>package</B> identifier <B>is</B>
{subprogram_declaration | type_declaration | subtype_declaration
| constant_declaration | signal_declaration | file_declaration
| alias_declaration | component_declaration
| attribute_declaration | attribute_specification
| disconnection_specification | use_clause
<U>| shared_variable_declaration | group_declaration</U>
<U>| group_template_declaration</U>}
<B>end</B> <U>[<B>package</B>]</U> [<I>package_</I>identifier] ;</PRE>
<P><P CLASS="Body"><A NAME="pgfId=254011"></A>You need a package body if
you declare any subprograms in the package declaration (a package declaration
and its body do not have to be in the same file):</P>
<PRE>package_body ::=
<B>package body</B> <I>package_</I>identifier is
{subprogram_declaration | subprogram_body
| type_declaration | subtype_declaration
| constant_declaration | file_declaration | alias_declaration
| use_clause
<U>| <I>shared_</I>variable_declaration | group_declaration</U>
<U>| group_template_declaration</U>}
<B>end</B> <U>[</U><B>package</B> <B>body</B><U>]</U> [<I>package_</I>identifier] ;</PRE>
<P><P CLASS="Body"><A NAME="pgfId=539560"></A>To make a package visible
[<A HREF="../../VHDL/LRM/HTML/1076_10.HTM#10.3">VHDL LRM10.3</A>] (or accessible,
so you can see and use the package and its contents), you must include a
library clause before a design unit and a use clause either before a design
unit or inside a unit, like this:</P>
<PRE><B>library</B> MyLib; -- library clause
<B>use</B> MyLib.MyPackage.<B>all</B>;<B> -</B>- use clause
-- design unit (entity + architecture, etc.) follows:</PRE>
<P><P CLASS="Body"><A NAME="pgfId=28395"></A>The <CODE>STD</CODE> and <CODE>WORK</CODE>
libraries and the <CODE>STANDARD</CODE> package are always visible. Things
that are visible to an entity are visible to its architecture bodies.</P>
<H3><A NAME="pgfId=1306"></A>10.6.1 Standard Package</H3>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=1334"></A>The VHDL STANDARD package
[<A HREF="../../VHDL/LRM/HTML/1076_14.HTM#14.2">VHDL LRM14.2</A>] is defined in
the LRM and implicitly declares the following implementation dependent types:
<CODE>TIME</CODE> , <CODE>INTEGER</CODE> , <CODE>REAL</CODE> . We shall
use uppercase for types defined in an IEEE standard package. Here is part
of the <CODE>STANDARD</CODE> package showing the explicit type and subtype
declarations:</P>
<PRE><B>package</B> Part_STANDARD <B>is</B>
<B>type</B> <CODE>BOOLEAN</CODE>
<B>is</B> (FALSE, TRUE); <B>type</B> <CODE>BIT</CODE>
<B>is</B> ('0', '1');
<B>type</B> <CODE>SEVERITY_LEVEL</CODE>
<B>is</B> (NOTE, WARNING, ERROR, FAILURE);
<B>subtype</B> <CODE>NATURAL</CODE>
<B>is</B> INTEGER <B>range</B> 0 <B>to</B> INTEGER'HIGH;
<B>subtype</B> <CODE>POSITIVE</CODE>
<B>is</B> INTEGER <B>range</B> 1 <B>to</B> INTEGER'HIGH;
<B>type</B> <CODE>BIT_VECTOR</CODE>
<B>is</B> <B>array</B> (NATURAL <B>range</B> <>) of BIT;
<B>type</B> <CODE>STRING</CODE>
<B>is</B> <B>array</B> (POSITIVE <B>range</B> <>) of CHARACTER;
-- the following declarations are VHDL-93 only:
<B>attribute</B> FOREIGN: STRING; -- for links to other languages
<B>subtype</B> DELAY_LENGTH <B>is</B> TIME <B>range</B> 0 fs <B>to</B> TIME'HIGH;
<B>type</B> FILE_OPEN_KIND <B>is</B> (READ_MODE,WRITE_MODE,APPEND_MODE);
<B>type</B> FILE_OPEN_STATUS <B>is</B>
(OPEN_OK,STATUS_ERROR,NAME_ERROR,MODE_ERROR);
<B>end</B> Part_STANDARD;</PRE>
<P><P CLASS="Body"><A NAME="pgfId=361356"></A>Notice that a <CODE>STRING</CODE>
array must have a positive index. The type <CODE>TIME</CODE> is declared
in the <CODE>STANDARD</CODE> package as follows:</P>
<PRE><B>type</B> TIME <B>is</B> <B>range</B> implementation_defined -- and varies with software
<B>units </B>fs; ps = 1000 fs; ns = 1000 ps; us = 1000 ns; ms = 1000 us;
sec = 1000 ms; min = 60 sec; hr = 60 min; <B>end</B> <B>units</B>;</PRE>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=361362"></A>The <CODE>STANDARD</CODE>
package also declares the function <CODE>now</CODE> that returns the current
simulation time (with type <CODE>TIME</CODE> in VHDL-87 and subtype <CODE>DELAY_LENGTH</CODE>
in VHDL-93).</P>
<P><P CLASS="Body"><A NAME="pgfId=361354"></A>In VHDL-93 the <CODE>CHARACTER</CODE>
type declaration extends the VHDL-87 declaration (the 128 ASCII characters):</P>
<PRE><B>type</B> Part_CHARACTER <B>is</B> ( -- 128 ASCII characters in VHDL-87
NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL, -- 33 control characters
BS, HT, LF, VT, FF, CR, SO, SI, -- including:
DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB, -- format effectors:
CAN, EM, SUB, ESC, FSP, GSP, RSP, USP, -- horizontal tab = HT
' ', '!', '"', '#', '$', '%', '&', ''', -- line feed = LF
'(', ')', '*', '+', ',', '-', '.', '/', -- vertical tab = VT
'0', '1', '2', '3', '4', '5', '6', '7', -- form feed = FF
'8', '9', ':', ';', '<', '=', '>', '?', -- carriage return = CR
'@', 'A', 'B', 'C', 'D', 'E', 'F', 'G', -- and others:
'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', -- FSP, GSP, RSP, USP use P
'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W', -- suffix to avoid conflict
'X', 'Y', 'Z', '[', '\', ']', '^', '_', -- with TIME units
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', DEL -- delete = DEL
-- VHDL-93 includes 96 more Latin-1 characters, like ¥ (Yen) and
-- 32 more control characters, better not to use any of them.
);</PRE>
<P><P CLASS="Body"><A NAME="pgfId=5560"></A>The VHDL-87 character set is
the 7-bit coded ISO 646-1983 standard known as the ASCII character set.
Each of the printable ASCII graphic character codes (there are 33 nonprintable
control codes, like <CODE>DEL</CODE> for delete) is represented by a graphic
symbol (the shapes of letters on the keyboard, on the display, and that
actually print). VHDL-93 uses the 8-bit coded character set ISO 8859-1:1987(E),
known as ISO Latin-1. The first 128 characters of the 256 characters in
ISO Latin-1 correspond to the 128-character ASCII code. The graphic symbols
for the printable ASCII characters are well defined, but not part of the
standard (for example, the shape of the graphic symbol that represents 'lowercase
a' is recognizable on every keyboard, display, and font). However, the graphic
symbols that represent the printable characters from other 128-character
codes of the ISO 8-bit character set are different in various fonts, languages,
and computer systems. For example, a pound sterling sign in a U.K. character
set looks like this-<CODE>'£'</CODE>, but in some fonts the same character
code prints as <CODE>'#'</CODE> (known as number sign, hash, or pound).
If you use such characters and want to share your models with people in
different countries, this can cause problems (you can see all 256 characters
in a character set by using Insert... Symbol in MS Word).</P>
<H3><A NAME="pgfId=5567"></A>10.6.2 Std_logic_1164 Package</H3>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=254891"></A>VHDL does not have
a built-in logic-value system. The <CODE>STANDARD</CODE> package predefines
the type <CODE>BIT</CODE> with two logic values, <CODE>'0'</CODE> and <CODE>'1'</CODE>
, but we normally need at least two more values: <CODE>'X'</CODE> (unknown)
and <CODE>'Z'</CODE> (high-impedance). Unknown is a metalogical value because
it does not exist in real hardware but is needed for simulation purposes.
We could define our own logic-value system with four logic values:</P>
<PRE><B>type</B> MVL4 <B>is</B> ('X', '0', '1', 'Z'); -- a four-value logic system</PRE>
<P><P CLASS="Body"><A NAME="pgfId=20881"></A>The proliferation of VHDL logic-value
systems prompted the creation of the Std_logic_1164 package (defined in
IEEE Std 1164-1993) that includes functions to perform logical, shift, resolution,
and conversion functions for types defined in the <CODE>Std_logic_1164</CODE>
system. To use this package in a design unit, you must include the following
library clause (before each design unit) and a use clause (either before
or inside the unit):</P>
<PRE><B>library</B> IEEE; <B>use</B> IEEE.std_logic_1164.<B>all</B>;</PRE>
<P><P CLASS="Body"><A NAME="pgfId=114157"></A>This <CODE>Std_Logic_1164</CODE>
package contains definitions for a nine-value logic system. The following
code and comments show the definitions and use of the most important parts
of the package <A HREF="#pgfId=539243" CLASS="footnote">1</A>:</P>
<PRE><B>package</B> Part_STD_LOGIC_1164 <B>is</B>
<B>type</B> STD_ULOGIC is
( 'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'W', -- Weak Unknown
'L', -- Weak 0
'H', -- Weak 1
'-' -- Don't Care);
<B>type</B> STD_ULOGIC_VECTOR <B>is</B> <B>array</B> (NATURAL <B>range</B> <>) <B>of</B> STD_ULOGIC;
<B>function</B> resolved (s : STD_ULOGIC_VECTOR) <B>return</B> STD_ULOGIC;
<B>subtype</B> STD_LOGIC <B>is</B> resolved STD_ULOGIC;
<B>type</B> STD_LOGIC_VECTOR <B>is</B> <B>array</B> (NATURAL <B>range</B> <>) <B>of</B> STD_LOGIC;
<B>subtype</B> X01 <B>is</B> resolved STD_ULOGIC <B>range</B> 'X' <B>to</B> '1';
<B>subtype</B> X01Z <B>is</B> resolved STD_ULOGIC <B>range</B> 'X' <B>to</B> 'Z';
<B>subtype</B> UX01 <B>is</B> resolved STD_ULOGIC <B>range</B> 'U' <B>to</B> '1';
<B>subtype</B> UX01Z <B>is</B> resolved STD_ULOGIC <B>range</B> 'U' <B>to</B> 'Z';
-- Vectorized overloaded logical operators:
<B>function</B> "and" (L : STD_ULOGIC; R : STD_ULOGIC) <B>return</B> UX01;
-- Logical operators not, and, nand, or, nor, xor, xnor (VHDL-93),
-- overloaded for STD_ULOGIC STD_ULOGIC_VECTOR STD_LOGIC_VECTOR.
-- Strength strippers and type conversion functions:
-- function To_T (X : F) return T;
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