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<H2>10.14 Execution</H2>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=281451"></A>Two successive statements
may execute in either a concurrent or sequential fashion depending on where
the statements appear.</P>
<PRE>statement_1; statement_2;</PRE>
<P><P CLASS="Body"><A NAME="pgfId=4681"></A>In sequential execution, <CODE>statement_1</CODE>
in this sequence is always evaluated before <CODE>statement 2</CODE>
. In concurrent execution, <CODE>statement_1</CODE> and <CODE>statement_2</CODE>
are evaluated at the same time (as far as we are concerned--obviously on
most computers exactly parallel execution is not possible). Concurrent execution
is the most important difference between VHDL and a computer programming
language. Suppose we have two signal assignment statements inside a <CODE>process</CODE>
statement. In this case <CODE>statement_1</CODE> and <CODE>statement_2</CODE>
are sequential assignment statements:</P>
<PRE><B>entity</B> Sequential_1 <B>is end</B>; <B>architecture</B> Behave <B>of</B> Sequential_1 <B>is</B>
<B>signal</B> s1, s2 : INTEGER := 0;
<B>begin </B>
<B> process</B> <B>begin</B>
s1 <= 1; -- sequential signal assignment 1
s2 <= s1 + 1; -- sequential signal assignment 2
<B>wait</B> <B>on</B> s1, s2 ;
<B> end</B> <B>process</B>;
<B>end</B>;
Time(fs) + Cycle s1 s2
---------------------- ------------ ------------
0+ 0: 0 0
0+ 1: * 1 * 1
0+ 2: * 1 * 2
0+ 3: * 1 * 2</PRE>
<P><P CLASS="Body"><A NAME="pgfId=252025"></A>If the two statements are
outside a <CODE>process</CODE> statement they are concurrent assignment
statements, as in the following example:</P>
<PRE><B>entity</B> Concurrent_1 <B>is</B> <B>end</B>; <B>architecture</B> Behave <B>of</B> Concurrent_1 <B>is</B>
<B>signal</B> s1, s2 : INTEGER := 0; <B>begin</B>
L1 : s1 <= 1; -- concurrent signal assignment 1
L2 : s2 <= s1 + 1; -- concurrent signal assignment 2
<B>end</B>;
Time(fs) + Cycle s1 s2
---------------------- ------------ ------------
0+ 0: 0 0
0+ 1: * 1 * 1
0+ 2: 1 * 2</PRE>
<P><P CLASS="Body"><A NAME="pgfId=252022"></A>The two concurrent signal
assignment statements in the previous example are equivalent to the two
processes, labeled as <CODE>P1</CODE> and <CODE>P2</CODE> , in the following
model.</P>
<PRE><B>entity</B> Concurrent_2 <B>is</B> <B>end</B>; <B>architecture</B> Behave <B>of</B> Concurrent_2 <B>is</B>
<B>signal</B> s1, s2 : INTEGER := 0; <B>begin</B>
P1 : <B>process</B> <B>begin </B>s1 <= 1; <B>wait</B> <B>on</B> s2 ; <B>end</B> <B>process</B>;
P2 : <B>process</B> <B>begin </B>s2 <= s1 + 1; <B>wait</B> <B>on</B> s1 ; <B>end</B> <B>process</B>;
<B>end</B>;
Time(fs) + Cycle s1 s2
---------------------- ------------ ------------
0+ 0: 0 0
0+ 1: * 1 * 1
0+ 2: * 1 * 2
0+ 3: * 1 2</PRE>
<P><P CLASS="Body"><A NAME="pgfId=4782"></A>Notice that the results are
the same (though the trace files are slightly different) for the architectures
<CODE>Sequential_1</CODE>, <CODE>Concurrent_1</CODE>, and <CODE>Concurrent_2</CODE>.
Updates to signals occur at the end of the simulation cycle, so the values
used will always be the old values. So far things seem fairly simple: We
have sequential execution or concurrent execution. However, variables are
updated immediately, so the variable values that are used are always the
new values. The examples in Table 10.17 illustrate this very important
difference.</P>
<P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
<TR>
<TD COLSPAN="3"><P CLASS="TableTitle"><A NAME="pgfId=405937"></A>TABLE 10.17 Variables
and signals in VHDL.</TD></TR>
<TR>
<TD COLSPAN="2"><P CLASS="Table"><A NAME="pgfId=405941"></A><P CLASS="TableHeads">Variables</TD>
<TD><P CLASS="Table"><A NAME="pgfId=405943"></A><P CLASS="TableHeads">Signals</TD></TR>
<TR>
<TD COLSPAN="2"><PRE><B>entity</B> Execute_1 <B>is end</B>;
<B>architecture</B> Behave <B>of</B> Execute_1 <B>is</B>
<B>begin </B>
<B> process</B>
<B> variable </B>v1 : INTEGER := 1;
<B> variable </B>v2 : INTEGER := 2;
<B> begin</B>
v1 := v2; -- before: v1 = 1, v2 = 2
v2 := v1; -- after: v1 = 2, v2 = 2
<B>wait</B>;
<B> end</B> <B>process</B>;
<B>end</B>;</PRE>
</TD>
<TD><PRE><B>entity</B> Execute_2 <B>is end</B>;
<B>architecture</B> Behave <B>of</B> Execute_2 <B>is</B>
<B>signal</B> s1 : INTEGER := 1;
<B>signal</B> s2 : INTEGER := 2;
<B>begin </B>
<B> process</B>
<B> begin</B>
s1 <= s2; -- before: s1 = 1, s2 = 2
s2 <= s1; -- after: s1 = 2, s2 = 1
<B>wait</B>;
<B> end</B> <B>process</B>;
<B>end</B>;</PRE>
</TD></TR>
</TABLE>
<P CLASS="Body"><A NAME="pgfId=6267"></A>The various concurrent and sequential
statements in VHDL are summarized in Table 10.18.</P>
<P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
<TR>
<TD COLSPAN="4"><P CLASS="TableTitle"><A NAME="pgfId=6274"></A>TABLE 10.18 Concurrent
and sequential statements in VHDL.</TD></TR>
<TR>
<TD COLSPAN="2"><P CLASS="Table"><A NAME="pgfId=6278"></A><P CLASS="TableHeads">Concurrent
[<A HREF="../../VHDL/LRM/HTML/1076_9.HTM#9">VHDL LRM9</A>]</TD>
<TD COLSPAN="2"><P CLASS="Table"><A NAME="pgfId=6280"></A><P CLASS="TableHeads">Sequential
[<A HREF="../../VHDL/LRM/HTML/1076_8.HTM#8">VHDL LRM8</A>]</TD></TR>
<TR>
<TD COLSPAN="2"><P><P CLASS="TableLeft"><A NAME="pgfId=6282"></A>block</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=6283"></A>process</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=6284"></A>concurrent_procedure_call</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=6285"></A>concurrent_assertion</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=6286"></A>concurrent_signal_assignment</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=6287"></A>component_instantiation</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=6288"></A>generate</TD>
<TD><P><P CLASS="TableLeft"><A NAME="pgfId=6290"></A>wait</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=6291"></A>assertion</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=6292"></A>signal_assignment</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=6293"></A>variable_assignment</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=6294"></A>procedure_call</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=6295"></A>if</TD>
<TD><P><P CLASS="TableLeft"><A NAME="pgfId=100586"></A>case</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=100565"></A>loop</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=100566"></A>next</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=100567"></A>exit</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=100568"></A>return</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=100569"></A>null</TD></TR>
</TABLE>
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