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<H2>10.17 Summary</H2>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=2187"></A>Table 10.27 shows
the essential elements of the VHDL language. Table 10.28 shows the
most important BNF definitions and their locations in this chapter. The
key points covered in this chapter are as follows:</P>
<UL>
<LI>The use of an <CODE>entity</CODE> and an <CODE>architecture</CODE>
<LI>The use of a <CODE>configuration</CODE> to bind entities and their
architectures
<LI>The compile, elaboration, initialization, and simulation steps
<LI>Types, subtypes, and their use in expressions
<LI>The logic systems based on <CODE>BIT</CODE> and <CODE>Std_Logic_1164</CODE>
types
<LI>The use of the IEEE synthesis packages for <CODE>BIT</CODE> arithmetic
<LI>Ports and port modes
<LI>Initial values and the difference between simulation and hardware
<LI>The difference between a <CODE>signal</CODE> and a <CODE>variable</CODE>
<LI>The different assignment statements and the timing of updates
<LI>The <CODE>process</CODE> and <CODE>wait</CODE> statements
</UL>
<P><P CLASS="Body"><A NAME="pgfId=222317"></A>VHDL is a "wordy"
language. The examples in this chapter are complete rather than code fragments.
To write VHDL "nicely," with indentation and nesting of constructs,
requires a large amount of space. Some of the VHDL code examples in this
chapter are deliberately dense (with reduced indentation and nesting), but
the bold keywords help you to see the code structure. Most of the time,
of course, we do not have the luxury of bold fonts (or color) to highlight
code. In this case, you should add additional space, indentation, nesting,
and comments.</P>
<P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
<TR>
<TD COLSPAN="4"><P CLASS="TableTitle"><A NAME="pgfId=537713"></A>TABLE 10.27 VHDL
summary.</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=537723"></A><P CLASS="TableHeads">VHDL feature</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537725"></A><P CLASS="TableHeads">Example</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537727"></A><P CLASS="TableHeads">Book</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537729"></A><P CLASS="TableHeads">93LRM</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=537731"></A>Comments</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=537733"></A>-- this is a comment</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537738"></A>10.3</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537740"></A><A HREF="../../VHDL/LRM/HTML/1076_13.HTM#13.8">13.8</A></TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=537742"></A>Literals (fixed-value items)</TD>
<TD><P><P CLASS="TableLeft"><A NAME="pgfId=537744"></A>12 1.0E6 '1' "110" 'Z'</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=537745"></A>2#1111_1111# "Hello
world"</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=537746"></A>STRING'("110")</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537751"></A>10.4</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537753"></A><A HREF="../../VHDL/LRM/HTML/1076_13.HTM#13.4">13.4</A></TD></TR>
<TR>
<TD><P><P CLASS="TableLeft"><A NAME="pgfId=537755"></A>Identifiers</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=537756"></A>(case-insensitive, start
with letter)</TD>
<TD><P><P CLASS="TableLeft"><A NAME="pgfId=537758"></A>a_good_name Same same</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=537759"></A>2_Bad bad_ _bad very__bad</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537764"></A>10.4</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537766"></A><A HREF="../../VHDL/LRM/HTML/1076_13.HTM#13.3">13.3</A></TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=537768"></A>Several basic units of code</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=537770"></A><B>entity</B> <B>
architecture</B> <B> configuration</B></TD>
<TD><P CLASS="Table"><A NAME="pgfId=537775"></A>10.5</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537777"></A><A HREF="../../VHDL/LRM/HTML/1076_1.HTM#1.1">1.1</A>-<A HREF="../../VHDL/LRM/HTML/1076_1.HTM#1.3">1.3</A></TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=537779"></A>Connections made through
ports</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=537781"></A><B>port</B> (<B> signal</B>
<B>in</B> i : BIT; <B>out</B> o : BIT);</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537786"></A>10.7</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537788"></A><A HREF="../../VHDL/LRM/HTML/1076_4.HTM#4.3">4.3</A></TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=537790"></A>Default expression</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=537792"></A><B>port</B> (i : BIT :=
'1'); <BR>
-- i='1' if left open</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537797"></A>10.7</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537799"></A><A HREF="../../VHDL/LRM/HTML/1076_4.HTM#4.3">4.3</A></TD></TR>
<TR>
<TD><P><P CLASS="TableLeft"><A NAME="pgfId=537801"></A>No built-in logic-value
system.</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=537802"></A>BIT and BIT_VECTOR (STD).</TD>
<TD><P><P CLASS="TableLeft"><A NAME="pgfId=537804"></A><B>type</B> BIT <B>is</B>
('0', '1'); -- predefined</P>
<PRE><A NAME="pgfId=537805"></A> <B>signal</B> myArray: BIT_VECTOR (7 <B>downto</B> 0);</PRE>
</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537810"></A>10.8</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537812"></A><A HREF="../../VHDL/LRM/HTML/1076_14.HTM#14.2">14.2</A></TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=537814"></A>Arrays</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=537816"></A>myArray(1 <B>downto</B>
0) <= ('0', '1');</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537821"></A>10.8</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537823"></A><A HREF="../../VHDL/LRM/HTML/1076_3.HTM#3.2.1">3.2.1</A></TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=537825"></A>Two basic types of logic
signals</TD>
<TD><P><P CLASS="TableLeft"><A NAME="pgfId=537827"></A>a <CODE>signal</CODE>
corresponds to a real wire</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=537828"></A>a <CODE>variable</CODE>
is a memory location in RAM</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537833"></A>10.9</TD>
<TD><P><P CLASS="Table"><A NAME="pgfId=537835"></A><A HREF="../../VHDL/LRM/HTML/1076_4.HTM#4.3.1.2">4.3.1.2</A></P>
<P><P CLASS="Table"><A NAME="pgfId=537836"></A><A HREF="../../VHDL/LRM/HTML/1076_4.HTM#4.3.1.3">4.3.1.3</A></TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=537838"></A>Types and explicit initial/default
value</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=537840"></A><B>signal </B>ONE : BIT
:= '1' ;</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537845"></A>10.9</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537847"></A><A HREF="../../VHDL/LRM/HTML/1076_4.HTM#4.3.2">4.3.2</A></TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=537849"></A>Implicit initial/default
value</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=537851"></A>BIT'LEFT = '0'</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537856"></A>10.9</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537858"></A><A HREF="../../VHDL/LRM/HTML/1076_4.HTM#4.3.2">4.3.2</A></TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=537860"></A>Predefined attributes</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=537862"></A><CODE>clk'EVENT, clk'STABLE</CODE></TD>
<TD><P CLASS="Table"><A NAME="pgfId=537867"></A>10.9.4</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537869"></A><A HREF="../../VHDL/LRM/HTML/1076_14.HTM#14.1">14.1</A></TD></TR>
<TR>
<TD><P><P CLASS="TableLeft"><A NAME="pgfId=537871"></A>Sequential statements
inside</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=537872"></A>processes model things
that happen one after another and repeat</TD>
<TD><P><P CLASS="TableLeft"><A NAME="pgfId=537874"></A><B>process</B> <B>begin</B></P>
<P><P CLASS="TableLeft"><A NAME="pgfId=537875"></A><B>wait</B> <B>until
</B>alarm = ring;<BR>
eat; work; sleep;</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=537876"></A><B>end</B> <B>process</B>;</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537881"></A>10.10</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537883"></A><A HREF="../../VHDL/LRM/HTML/1076_8.HTM#8">8</A></TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=537885"></A>Timing with wait statement</TD>
<TD><P><P CLASS="TableLeft"><A NAME="pgfId=537887"></A><B>wait</B><CODE> </CODE><B>for</B><CODE>
1 ns; -- not wait 1 ns</CODE></P>
<P><P CLASS="TableLeft"><A NAME="pgfId=537888"></A><B>wait</B> <B>on</B>
light <B>until</B> light = green;</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537893"></A>10.10.1</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537895"></A><A HREF="../../VHDL/LRM/HTML/1076_8.HTM#8.1">8.1</A></TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=537897"></A>Update to signals occurs
at the end of a simulation cycle</TD>
<TD><P><P CLASS="TableLeft"><A NAME="pgfId=537899"></A>signal <= 1; -- delta
time delay</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=537900"></A>signal <= variable1
<B>after</B> 2 ns;</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537905"></A>10.10.3</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537907"></A><A HREF="../../VHDL/LRM/HTML/1076_8.HTM#8.3">8.3</A></TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=537909"></A>Update to variables is immediate</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=537911"></A>variable := 1; -- immediate
update</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537916"></A>10.10.3</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537918"></A><A HREF="../../VHDL/LRM/HTML/1076_8.HTM#8.4">8.4</A></TD></TR>
<TR>
<TD><P><P CLASS="TableLeft"><A NAME="pgfId=537920"></A>Processes and concurrent</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=537921"></A>statements model things
that happen at the same time</TD>
<TD><P><P CLASS="TableLeft"><A NAME="pgfId=537923"></A><B>process</B><CODE>
</CODE><B>begin</B><CODE> rain ; </CODE><B>end</B><CODE> </CODE><B>process</B><CODE>
;</CODE></P>
<P><P CLASS="TableLeft"><A NAME="pgfId=537924"></A><B>process</B><CODE>
</CODE><B>begin</B><CODE> sing ; </CODE><B>end</B><CODE> </CODE><B>process</B><CODE>
;</CODE></P>
<P><P CLASS="TableLeft"><A NAME="pgfId=537925"></A><B>process</B><CODE>
</CODE><B>begin</B><CODE> dance; </CODE><B>end</B><CODE> </CODE><B>process</B><CODE>
;</CODE></TD>
<TD><P CLASS="Table"><A NAME="pgfId=537930"></A>10.13</TD>
<TD><P CLASS="Table"><A NAME="pgfId=537932"></A><A HREF="../../VHDL/LRM/HTML/1076_9.HTM#9.2">9.2</A></TD></TR>
<TR>
<TD><P><P CLASS="TableLeft"><A NAME="pgfId=537934"></A>IEEE Std_Logic_1164</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=537935"></A>(defines logic operators
on 1164 types)</TD>
<TD><PRE><A NAME="pgfId=537937"></A> <CODE>STD_ULOGIC</CODE>
, <CODE>STD_LOGIC</CODE>
, <CODE>STD_ULOGIC_VECTOR</CODE>
, and <CODE>STD_LOGIC_VECTOR</CODE>
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