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<H2>10.1 A Counter</H2>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=339767"></A>The following VHDL
model describes an electrical "black box" that contains a 50 MHz
clock generator and a counter. The counter increments on the negative edge
of the clock, counting from zero to seven, and then begins at zero again.
The model contains separate processes that execute at the same time as each
other. Modeling concurrent execution is the major difference between HDLs
and computer programming languages such as C.</P>
<PRE><B>entity</B> Counter_1 <B>is end</B>; -- declare a "black box" called Counter_1
<B>library</B> STD; <B>use</B> STD.TEXTIO.<B>all</B>; -- we need this library to print
<B>architecture</B> Behave_1 <B>of</B> Counter_1 <B>is </B>-- describe the "black box"
-- declare a signal for the clock, type BIT, initial value '0'
<B> signal</B> Clock : BIT := '0';
-- declare a signal for the count, type INTEGER, initial value 0
<B> signal</B> Count : INTEGER := 0;
<B>begin </B>
<B> process</B> <B>begin </B>-- process to generate the clock
<B> wait</B> <B>for</B> 10 ns; -- a delay of 10 ns is half the clock cycle
Clock <= <B>not</B> Clock;
<B> if</B> (now > 340 ns) <B>then</B> <B>wait</B>; <B>end</B> <B>if</B>; -- stop after 340 ns
<B>end</B> <B>process</B>;
-- process to do the counting, runs concurrently with other processes
<B>process</B> <B>begin</B>
-- wait here until the clock goes from 1 to 0
<B>wait</B> <B>until</B> (Clock = '0');
-- now handle the counting
<B>if</B> (Count = 7) <B>then</B> Count <= 0;
<B>else</B> Count <= Count + 1;
<B>end</B> <B>if</B>;
<B>end</B> <B>process</B>;
<B>process</B> (Count) <B>variable</B> L: LINE; <B>begin</B> -- process to print
write(L, now); write(L, STRING'(" Count="));
write(L, Count); writeline(output, L);
<B>end</B> <B>process</B>;
<B>end</B>;</PRE>
<P><P CLASS="Body"><A NAME="pgfId=112278"></A>Throughout this book VHDL
keywords (reserved words that are part of the language) are shown in bold
type in code examples (but not in the text). The code examples use the bold
keywords to improve readability. VHDL code is often lengthy and the code
in this book is always complete wherever possible. In order to save space
many of the code examples do not use the conventional spacing and formatting
that is normally considered good practice. So "Do as I say and not
as I do."</P>
<P><P CLASS="Body"><A NAME="pgfId=358942"></A>The steps to simulate the
model and the printed results for <CODE>Counter_1</CODE> using the Model
Technology V-System/Plus common-kernel simulator are as follows:</P>
<PRE>> vlib work
> vcom Counter_1.vhd
Model Technology VCOM V-System VHDL/Verilog 4.5b
-- Loading package standard
-- Compiling entity counter_1
-- Loading package textio
-- Compiling architecture behave_1 of counter_1
> vsim -c counter_1
# Loading /../std.standard
# Loading /../std.textio(body)
# Loading work.counter_1(behave_1)
VSIM 1> run 500
# 0 ns Count=0
# 20 ns Count=1
(...15 lines omitted...)
# 340 ns Count=1
VSIM 2> quit
></PRE>
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