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<TITLE>ASICs CHAPTER 10: VHDL </TITLE>
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<H3>CHAPTER 10<BR>
VHDL</H3>
<P><P CLASS="BodyAfterHead">The U.S. Department of Defense (DoD) supported
the development of VHDL (VHSIC hardware description language) as part of
the VHSIC (very high-speed IC) program in the early 1980s. The companies
in the VHSIC program found they needed something more than schematic entry
to describe large ASICs, and proposed the creation of a hardware description
language. VHDL was then handed over to the Institute of Electrical and Electronics
Engineers (IEEE) in order to develop and approve the IEEE Standard 1076-1987.
<A HREF="#pgfId=539086" CLASS="footnote">1</A> As part of its standardization
process the DoD has specified the use of VHDL as the documentation, simulation,
and verification medium for ASICs (MIL-STD-454). Partly for this reason
VHDL has gained rapid acceptance, initially for description and documentation,
and then for design entry, simulation, and synthesis as well.</P>
<P><P CLASS="Body"><A NAME="pgfId=88156"></A>The first revision of the 1076
standard was approved in 1993. References to the VHDL Language Reference
Manual (LRM) in this chapter--[VHDL 87LRM2.1, <A HREF="../../VHDL/LRM/HTML/1076_2.HTM#2.2">93LRM2.2</A>]
for example--point to the 1987 and 1993 versions of the LRM [IEEE, 1076-1987
and 1076-1993]. The prefixes 87 and 93 are omitted if the references are
the same in both editions. Technically 1076-1987 (known as VHDL-87) is now
obsolete and replaced by 1076-1993 (known as VHDL-93). Except for code that
is marked <CODE>'VHDL-93 only'</CODE> the examples in this chapter
can be analyzed (the VHDL word for "compiled") and simulated using
both VHDL-87 and VHDL-93 systems.</P>
<P><A HREF="CH10.01.htm#pgfId=83948" CLASS="Hypertext">10.1 A Counter</A></P>
<P><A HREF="CH10.02.htm#pgfId=106926" CLASS="Hypertext">10.2 A 4-bit
Multiplier</A></P>
<P><A HREF="CH10.03.htm#pgfId=325261" CLASS="Hypertext">10.3 Syntax
and Semantics of VHDL</A></P>
<P><A HREF="CH10.04.htm#pgfId=14404" CLASS="Hypertext">10.4 Identifiers
and Literals </A></P>
<P><A HREF="CH10.05.htm#pgfId=112386" CLASS="Hypertext">10.5 Entities
and Architectures</A></P>
<P><A HREF="CH10.06.htm#pgfId=28273" CLASS="Hypertext">10.6 Packages
and Libraries</A></P>
<P><A HREF="CH10.07.htm#pgfId=16879" CLASS="Hypertext">10.7 Interface
Declarations</A></P>
<P><A HREF="CH10.08.htm#pgfId=10949" CLASS="Hypertext">10.8 Type Declarations</A></P>
<P><A HREF="CH10.09.htm#pgfId=10666" CLASS="Hypertext">10.9 Other
Declarations</A></P>
<P><A HREF="CH10.10.htm#pgfId=178976" CLASS="Hypertext">10.10 Sequential
Statements</A></P>
<P><A HREF="CH10.11.htm#pgfId=7750" CLASS="Hypertext">10.11 Operators</A></P>
<P><A HREF="CH10.12.htm#pgfId=200123" CLASS="Hypertext">10.12 Arithmetic</A></P>
<P><A HREF="CH10.13.htm#pgfId=219992" CLASS="Hypertext">10.13 Concurrent
Statements</A></P>
<P><A HREF="CH10.14.htm#pgfId=25138" CLASS="Hypertext">10.14 Execution</A></P>
<P><A HREF="CH10.15.htm#pgfId=2157" CLASS="Hypertext">10.15 Configurations
and Specifications</A></P>
<P><A HREF="CH10.16.htm#pgfId=65561" CLASS="Hypertext">10.16 An Engine
Controller</A></P>
<P><A HREF="CH10.17.htm#pgfId=446019" CLASS="Hypertext">10.17 Summary</A></P>
<P><A HREF="CH10.18.htm#pgfId=2203" CLASS="Hypertext">10.18 Problems</A></P>
<P><A HREF="CH10.19.htm#pgfId=538620" CLASS="Hypertext">10.19 Bibliography</A></P>
<P><A HREF="CH10.20.htm#pgfId=538731" CLASS="Hypertext">10.20 References</A></P>
<P><HR ALIGN="LEFT"><P CLASS="Footnote2"><SPAN CLASS="footnoteNumber"> 1.</SPAN>
<A NAME="pgfId=539086"></A>Some of the material in this chapter is reprinted
with permission from IEEE Std 1076-1993, © 1993 IEEE. All rights reserved.
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