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<H2>10.2 A 4-bit Multiplier</H2>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=282579"></A>This section presents
a more complex VHDL example to motivate the study of the syntax and semantics
of VHDL in the rest of this chapter.</P>
<H3><A NAME="pgfId=278898"></A>10.2.1 An 8-bit Adder</H3>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=344218"></A>Table 10.1 shows
a VHDL model for the full adder that we described in Section 2.6, "Datapath
Logic Cells." Table 10.2 shows a VHDL model for an 8-bit ripple-carry
adder that uses eight instances of the full adder.</P>
<P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
<TR>
<TH COLSPAN="2" ALIGN="LEFT"><P ALIGN=LEFT><P CLASS="TableTitle"><A NAME="pgfId=339672"></A>TABLE 10.1 A
full adder.</TH></TR>
<TR>
<TD ROWSPAN="2"><PRE><B>entity</B> Full_Adder <B>is</B>
<B>generic</B> (TS : TIME := 0.11 ns; TC : TIME := 0.1 ns);
<B>port</B> (X, Y, Cin: <B>in</B> BIT; Cout, Sum: <B>out</B> BIT);
<B>end</B> Full_Adder;
<B>architecture</B> Behave <B>of</B> Full_Adder <B>is</B>
<B>begin</B>
Sum <= X <B>xor</B> Y <B>xor</B> Cin <B>after</B> TS;
Cout <= (X <B>and</B> Y) <B>or</B> (X <B>and</B> Cin) <B>or</B> (Y <B>and</B> Cin) <B>after</B> TC;
<B>end</B>;</PRE>
</TD>
<TD><P><P CLASS="Table"><A NAME="pgfId=339689"></A><P CLASS="Superscript"></P>
<P> </P>
<P><IMG SRC="CH10-1.gif" WIDTH="96" HEIGHT="66" NATURALSIZEFLAG="3" ALIGN=
"BOTTOM"></TD></TR>
<TR>
<TD><P><P CLASS="TableLeft"><A NAME="pgfId=339693"></A>Timing:</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=339694"></A>TS (Input to Sum) = 0.1
1 ns</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=339695"></A>TC (Input to Cout) =
0.1 ns</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=536836"></A> </TD></TR>
</TABLE>
<TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
<TR>
<TH COLSPAN="2" ALIGN="LEFT"><P ALIGN=LEFT><P CLASS="TableTitle"><A NAME="pgfId=339706"></A>TABLE 10.2 An
8-bit ripple-carry adder.</TH></TR>
<TR>
<TD><PRE><B>entity</B> Adder8 <B>is</B>
<B>port</B> (A, B: <B>in</B> BIT_VECTOR(7 <B>downto</B> 0);
Cin: <B>in</B> BIT; Cout: <B>out</B> BIT;
Sum: <B>out</B> BIT_VECTOR(7 <B>downto</B> 0));
<B>end</B> Adder8;
<B>architecture</B> Structure <B>of</B> Adder8 <B>is</B>
<B>component</B> Full_Adder
<B>port</B> (X, Y, Cin: <B>in</B> BIT; Cout, Sum: <B>out</B> BIT);
<B>end</B> <B>component</B>;
<B>signal</B> C: BIT_VECTOR(7 <B>downto</B> 0);
<B>begin </B>
Stages: <B>for</B> i <B>in</B> 7 <B>downto</B> 0 <B>generate</B>
LowBit: <B>if</B> i = 0 <B>generate</B>
FA:Full_Adder <B>port</B> <B>map</B> (A(0),B(0),Cin,C(0),Sum(0));
<B>end</B> <B>generate</B>;
OtherBits: <B>if</B> i /= 0 <B>generate</B>
FA:Full_Adder <B>port</B> <B>map</B>
(A(i),B(i),C(i-1),C(i),Sum(i));
<B>end</B> <B>generate</B>;
<B>end</B> <B>generate</B>;
Cout <= C(7);
<B>end</B>;</PRE>
</TD>
<TD><P><P CLASS="Table"><A NAME="pgfId=339736"></A><P CLASS="Superscript"></P>
<P> </P>
<P><IMG SRC="CH10-2.gif" WIDTH="110" HEIGHT="278" NATURALSIZEFLAG="3" ALIGN=
"BOTTOM"></TD></TR>
</TABLE>
</P>
<H3><A NAME="pgfId=323454"></A>10.2.2 A Register Accumulator</H3>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=344628"></A>Table 10.3 shows
a VHDL model for a positive-edge-triggered D flip-flop with an active-high
asynchronous clear. Table 10.4 shows an 8-bit register that uses this
D flip-flop model (this model only provides the <CODE>Q</CODE> output from
the register and leaves the <CODE>QN</CODE> flip-flop outputs unconnected).</P>
<P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
<TR>
<TH COLSPAN="2" ALIGN="LEFT"><P ALIGN=LEFT><P CLASS="TableTitle"><A NAME="pgfId=307952"></A>TABLE 10.3 Positive-edge-triggered
D flip-flop with asynchronous clear.</TH></TR>
<TR>
<TD ROWSPAN="2"><PRE><B>entity</B> DFFClr <B>is</B>
<B>generic</B>(TRQ : TIME := 2 ns; TCQ : TIME := 2 ns);
<B>port</B> (CLR, CLK, D : <B>in</B> BIT; Q, QB : <B>out</B> BIT);
<B>end</B>;
<B>architecture</B> Behave <B>of</B> DFFClr <B>is</B>
<B>signal</B> Qi : BIT;
<B>begin</B> QB <= <B>not</B> Qi; Q <= Qi;
<B>process</B> (CLR, CLK) <B>begin</B>
<B>if</B> CLR = '1' <B>then</B> Qi <= '0' <B>after</B> TRQ;
<B>elsif</B> CLK'EVENT <B>and</B> CLK = '1'
<B> then</B> Qi <= D <B>after</B> TCQ;
<B> end</B> <B>if</B>;
<B>end</B> <B>process</B>;
<B>end</B>;</PRE>
</TD>
<TD><P><P CLASS="Table"><A NAME="pgfId=307974"></A><P CLASS="Superscript"></P>
<P> </P>
<P><IMG SRC="CH10-3.gif" WIDTH="77" HEIGHT="86" NATURALSIZEFLAG="3" ALIGN=
"BOTTOM"></TD></TR>
<TR>
<TD><P><P CLASS="TableLeft"><A NAME="pgfId=307978"></A>Timing:</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=307979"></A><CODE>TRQ</CODE> (CLR
to Q/QN) = 2 ns</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=307980"></A><CODE>TCQ</CODE> (CLK
to Q/QN) = 2 ns</TD></TR>
</TABLE>
<TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
<TR>
<TH COLSPAN="2" ALIGN="LEFT"><P ALIGN=LEFT><P CLASS="TableTitle"><A NAME="pgfId=307993"></A>TABLE 10.4 An
8-bit register.</TH></TR>
<TR>
<TD ROWSPAN="2"><PRE><B>entity</B> Register8 <B>is</B>
<B> port</B> (D : <B>in</B> BIT_VECTOR(7 <B>downto</B> 0);
Clk, Clr: <B>in</B> BIT ; Q : <B>out</B> BIT_VECTOR(7 <B>downto</B> 0));
<B>end</B>;
<B>architecture</B> Structure <B>of</B> Register8 <B>is</B>
<B>component </B>DFFClr
<B>port</B> (Clr, Clk, D : <B>in</B> BIT; Q, QB : <B>out</B> BIT);
<B>end</B> <B>component</B>;
<B>begin</B>
STAGES: <B>for</B> i <B>in</B> 7 <B>downto</B> 0 <B>generate</B>
FF: DFFClr <B>port</B> <B>map</B> (Clr, Clk, D(i), Q(i), <B>open</B>);
<B>end</B> <B>generate</B>;
<B>end</B>;</PRE>
</TD>
<TD><P><P CLASS="Table"><A NAME="pgfId=308014"></A><P CLASS="Superscript"></P>
<P> </P>
<P><IMG SRC="CH10-4.gif" WIDTH="77" HEIGHT="86" NATURALSIZEFLAG="3" ALIGN=
"BOTTOM"></TD></TR>
<TR>
<TD><P><P CLASS="TableLeft"><A NAME="pgfId=308018"></A>8-bit register. Uses</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=308019"></A>DFFClr positive edge-triggered
flip-flop model.</TD></TR>
</TABLE>
<P CLASS="Body"><A NAME="pgfId=307947"></A>Table 10.5 shows a model
for a datapath multiplexer that consists of eight 2:1 multiplexers with
a common select input (this select signal would normally be a control signal
in a datapath). The multiplier will use the register and multiplexer components
to implement a register accumulator.</P>
<P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
<TR>
<TH COLSPAN="2" ALIGN="LEFT"><P ALIGN=LEFT><P CLASS="TableTitle"><A NAME="pgfId=308028"></A>TABLE 10.5 An
8-bit multiplexer.</TH></TR>
<TR>
<TD ROWSPAN="2"><PRE><B>entity</B> Mux8 <B>is</B>
<B>generic</B> (TPD : TIME := 1 ns);
<B> port</B> (A, B : <B>in</B> BIT_VECTOR (7 <B>downto</B> 0);
Sel : <B>in</B> BIT := '0'; Y : <B>out</B> BIT_VECTOR (7 <B>downto</B> 0));
<B>end</B>;
<B>architecture</B> Behave <B>of</B> Mux8 <B>is</B>
<B>begin</B>
Y <= A <B>after</B> TPD <B>when</B> Sel = '1' <B>else</B> B <B>after</B> TPD;
<B>end</B>;</PRE>
</TD>
<TD><P><P CLASS="Table"><A NAME="pgfId=308045"></A><P CLASS="Superscript"></P>
<P> </P>
<P><IMG SRC="CH10-5.gif" WIDTH="74" HEIGHT="50" NATURALSIZEFLAG="3" ALIGN=
"BOTTOM"></TD></TR>
<TR>
<TD><P><P CLASS="TableLeft"><A NAME="pgfId=308049"></A>Eight 2:1 MUXs with</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=308050"></A>single select input.</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=308051"></A>Timing:</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=308052"></A><CODE>TPD</CODE> (input
to Y) = 1 ns</TD></TR>
</TABLE>
</P>
<H3><A NAME="pgfId=308054"></A>10.2.3 Zero Detector</H3>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=292438"></A>Table 10.6 shows
a model for a variable-width zero detector that accepts a bus of any width
and will produce a single-bit output of <CODE>'1'</CODE> if all input bits
are zero.</P>
<P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
<TR>
<TH COLSPAN="2" ALIGN="LEFT"><P ALIGN=LEFT><P CLASS="TableTitle"><A NAME="pgfId=292442"></A>TABLE 10.6 A
zero detector.</TH></TR>
<TR>
<TD ROWSPAN="2"><PRE><B>entity</B> AllZero <B>is</B>
<B>generic</B> (TPD : TIME := 1 ns);
<B>port</B> (X : BIT_VECTOR; F : <B>out </B>BIT );
<B>end</B>;
<B>architecture</B> Behave <B>of</B> AllZero <B>is</B>
<B>begin</B> <B>process</B> (X) <B>begin</B> F <= '1' <B>after</B> TPD;
<B>for</B> j <B>in</B> X'RANGE <B>loop</B>
<B>if</B> X(j) = '1' <B>then </B>F <= '0' <B>after</B> TPD; <B>end</B> <B>if</B>;
<B>end</B> <B>loop</B>;
<B>end</B> <B>process</B>;
<B>end</B>;</PRE>
</TD>
<TD><P><P CLASS="Table"><A NAME="pgfId=292459"></A><P CLASS="Superscript"></P>
<P> </P>
<P><IMG SRC="CH10-6.gif" WIDTH="65" HEIGHT="42" NATURALSIZEFLAG="3" ALIGN=
"BOTTOM"></TD></TR>
<TR>
<TD><P><P CLASS="TableLeft"><A NAME="pgfId=292463"></A>Variable-width zero detector.</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=293245"></A>Timing:</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=293246"></A><CODE>TPD</CODE> (X to
F) = 1 ns</TD></TR>
</TABLE>
</P>
<H3><A NAME="pgfId=292432"></A>10.2.4 A Shift Register</H3>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=279265"></A>Table 10.7 shows
a variable-width shift register that shifts (left or right under input control,
<CODE>DIR</CODE> ) on the positive edge of the clock, <CODE>CLK</CODE> ,
gated by a shift enable, <CODE>SH</CODE> . The parallel load, <CODE>LD</CODE>
, is synchronous and aligns the input LSB to the LSB of the output, filling
unused MSBs with zero. Bits vacated during shifts are zero filled. The clear,
<CODE>CLR</CODE> , is asynchronous.</P>
<P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
<TR>
<TH COLSPAN="2" ALIGN="LEFT"><P ALIGN=LEFT><P CLASS="TableTitle"><A NAME="pgfId=279245"></A>TABLE 10.7 A
variable-width shift register.</TH></TR>
<TR>
<TD ROWSPAN="2"><PRE><B>entity</B> ShiftN <B>is</B>
<B>generic </B>(TCQ : TIME := 0.3 ns; TLQ : TIME := 0.5 ns;
TSQ : TIME := 0.7 ns);
<B>port</B>(CLK, CLR, LD, SH, DIR: <B>in</B> BIT;
D: <B>in</B> BIT_VECTOR; Q: <B>out</B> BIT_VECTOR);
<B> begin</B> <B>assert</B> (D'LENGTH <= Q'LENGTH)
<B>report</B> "D wider than output Q" <B>severity</B> Failure;
<B>end</B> ShiftN;
<B>architecture</B> Behave <B>of</B> ShiftN <B>is</B>
<B>begin</B> Shift: <B>process</B> (CLR, CLK)
<B>subtype</B> InB <B>is</B> NATURAL <B>range</B> D'LENGTH-1 <B>downto</B> 0;
<B>subtype</B> OutB <B>is</B> NATURAL <B>range</B> Q'LENGTH-1 <B>downto</B> 0;
<B>variable</B> St: BIT_VECTOR(OutB);
<B>begin</B>
<B>if</B> CLR = '1' <B>then</B>
St := (<B>others</B> => '0'); Q <= St <B>after</B> TCQ;
<B>elsif</B> CLK'EVENT <B>and</B> CLK='1' <B>then</B>
<B>if</B> LD = '1' <B>then</B>
St := (<B>others</B> => '0');
St(InB) := D;
Q <= St <B>after</B> TLQ;
<B>elsif</B> SH = '1' <B>then</B>
<B>case</B> DIR <B>is</B>
<B>when</B> '0' => St := '0' & St(St'LEFT <B>downto</B> 1);
<B>when</B> '1' => St := St(St'LEFT-1 <B>downto</B> 0) & '0';
<B>end</B> <B>case</B>;
Q <= St <B>after</B> TSQ;
<B>end</B> <B>if</B>;
<B>end</B> <B>if</B>;
<B>end</B> <B>process</B>;
<B>end</B>;</PRE>
</TD>
<TD><P><P CLASS="Table"><A NAME="pgfId=279264"></A><P CLASS="Superscript"></P>
<P> </P>
<P><IMG SRC="CH10-7.gif" WIDTH="113" HEIGHT="96" NATURALSIZEFLAG="3" ALIGN=
"BOTTOM"></TD></TR>
<TR>
<TD><P><P CLASS="TableLeft"><A NAME="pgfId=282409"></A>CLK Clock</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=282413"></A>CLR Clear, active high</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=282417"></A>LD Load, active high</P>
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