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<H2>10.15 Configurations and Specifications</H2>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=3660"></A>The difference between,
the interaction, and the use of component/configuration declarations and
specifications is probably the most confusing aspect of VHDL. Fortunately
this aspect of VHDL is not normally important for ASIC design. The syntax
of component/configuration declarations and specifications is shown in Table 10.19.</P>
<P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
<TR>
<TD COLSPAN="2"><P CLASS="TableTitle"><A NAME="pgfId=426036"></A>TABLE 10.19 VHDL
binding.</TD></TR>
<TR>
<TD VALIGN="TOP"><PRE><A NAME="pgfId=425939"></A>configuration
<A NAME="pgfId=425940"></A>declaration <A HREF="#pgfId=426042" CLASS="footnote">1</A>
<A NAME="pgfId=571279"></A>[<A HREF="../../VHDL/LRM/HTML/1076_1.HTM#1.3">VHDL LRM1.3</A>]</PRE>
</TD>
<TD VALIGN="TOP"><PRE><A NAME="pgfId=539794"></A><B>configuration</B> identifier <B>of</B> <I>entity_</I>name <B>is</B>
<A NAME="pgfId=539795"></A> {use_clause|attribute_specification<U>|group_declaration</U>}
<A NAME="pgfId=539796"></A> block_configuration
<A NAME="pgfId=539797"></A><B>end</B> <U>[<B>configuration</B>]</U> [<I>configuration_</I>identifier];</PRE>
</TD></TR>
<TR>
<TD VALIGN="TOP"><PRE><A NAME="pgfId=425948"></A>block
<A NAME="pgfId=425949"></A>configuration
<A NAME="pgfId=571280"></A>[<A HREF="../../VHDL/LRM/HTML/1076_1.HTM#1.3.1">VHDL LRM1.3.1</A>]</PRE>
</TD>
<TD VALIGN="TOP"><PRE><A NAME="pgfId=539799"></A><B>for</B> <I>architecture_</I>name
<A NAME="pgfId=539800"></A> |<I>block_statement_</I>label
<A NAME="pgfId=539801"></A> |<I>generate_statement_</I>label [(index_specification)]
<A NAME="pgfId=539802"></A>{<B>use</B> selected_name {, selected_name};}
<A NAME="pgfId=539803"></A>{block_configuration|component_configuration}
<A NAME="pgfId=539804"></A><B>end</B> <B>for</B> ;</PRE>
</TD></TR>
<TR>
<TD VALIGN="TOP"><PRE><A NAME="pgfId=425959"></A>configuration
<A NAME="pgfId=425960"></A>specification <A HREF="#pgfId=426042" CLASS="footnote">1</A>
<A NAME="pgfId=571285"></A>[<A HREF="../../VHDL/LRM/HTML/1076_5.HTM#5.2">VHDL LRM5.2</A>]</PRE>
</TD>
<TD VALIGN="TOP"><PRE><A NAME="pgfId=539806"></A><B>for</B>
<A NAME="pgfId=539807"></A> <I>instantiation_</I>label{,<I>instantiation_</I>label}:<I>component_</I>name
<A NAME="pgfId=539808"></A> |<B>others</B>:<I>component_</I>name
<A NAME="pgfId=539809"></A> |<B>all</B>:<I>component_</I>name
<A NAME="pgfId=539810"></A>[<B>use</B>
<A NAME="pgfId=539811"></A> <B>entity</B> <I>entity_</I>name [(<I>architecture_</I>identifier)]
<A NAME="pgfId=539812"></A> |<B>configuration</B> <I>configuration_</I>name
<A NAME="pgfId=539813"></A> |<B>open</B>]
<A NAME="pgfId=539814"></A>[<B>generic</B> <B>map</B> (<I>generic_</I>association_list)]
<A NAME="pgfId=539815"></A>[<B>port</B> <B>map</B> (<I>port_</I>association_list)];</PRE>
</TD></TR>
<TR>
<TD VALIGN="TOP"><PRE><A NAME="pgfId=425974"></A>component
<A NAME="pgfId=425975"></A>declaration <A HREF="#pgfId=426042" CLASS="footnote">1</A>
<A NAME="pgfId=571292"></A>[<A HREF="../../VHDL/LRM/HTML/1076_4.HTM#4.5">VHDL LRM4.5</A>]</PRE>
</TD>
<TD VALIGN="TOP"><PRE><A NAME="pgfId=539817"></A><B>component</B> identifier <U>[<B>is</B>]</U>
<A NAME="pgfId=539818"></A> [<B>generic</B> (<I>local_generic_</I>interface_list);]
<A NAME="pgfId=539819"></A> [<B>port</B> (<I>local_port_</I>interface_list);]
<A NAME="pgfId=539820"></A><B>end</B> <B>component</B> <U>[<I>component_</I>identifier]</U>;</PRE>
</TD></TR>
<TR>
<TD VALIGN="TOP"><PRE><A NAME="pgfId=425983"></A>component
<A NAME="pgfId=425984"></A>configuration <A HREF="#pgfId=426042" CLASS="footnote">1</A>
<A NAME="pgfId=571297"></A>[<A HREF="../../VHDL/LRM/HTML/1076_1.HTM#1.3.2">VHDL LRM1.3.2</A>]</PRE>
</TD>
<TD VALIGN="TOP"><PRE><A NAME="pgfId=539822"></A><B>for</B>
<A NAME="pgfId=539823"></A><I>instantiation_</I>label {, <I>instantiation_</I>label}:<I>component_</I>name
<A NAME="pgfId=539824"></A>|<B>others</B>:<I>component_</I>name
<A NAME="pgfId=539825"></A>|<B>all</B>:<I>component_</I>name
<A NAME="pgfId=539826"></A>[<U>[</U><B>use</B>
<A NAME="pgfId=539827"></A> <B>entity</B> <I>entity_</I>name [(<I>architecture_</I>identifier)]
<A NAME="pgfId=539828"></A> |<B>configuration</B> <I>configuration_</I>name
<A NAME="pgfId=539829"></A> |<B>open</B><U>]</U>
<A NAME="pgfId=539830"></A> [<B>generic</B> <B>map</B> (<I>generic_</I>association_list)]
<A NAME="pgfId=539831"></A> [<B>port</B> <B>map</B> (<I>port_</I>association_list)];]
<A NAME="pgfId=539832"></A>[block_configuration]
<A NAME="pgfId=539833"></A><B>end</B> <B>for</B>;</PRE>
<P> </TD></TR>
</TABLE>
</P>
<UL>
<LI><A NAME="pgfId=241938"></A>A configuration declaration defines a configuration--it
is a library unit and is one of the basic units of VHDL code.
<LI><A NAME="pgfId=241952"></A>A block configuration defines the configuration
of a block statement or a design entity. A block configuration appears
inside a configuration declaration, a component configuration, or nested
in another block configuration.
<LI><A NAME="pgfId=241936"></A>A configuration specification may appear
in the declarative region of a generate statement, block statement, or
architecture body.
<LI><A NAME="pgfId=241946"></A>A component declaration may appear in the
declarative region of a generate statement, block statement, architecture
body, or package.
<LI><A NAME="pgfId=241962"></A>A component configuration defines the configuration
of a component and appears in a block configuration.
</UL>
<P><P CLASS="Body"><A NAME="pgfId=406896"></A>Table 10.20 shows a simple
example (identical in structure to the example of Section 10.5) that
illustrates the use of each of the preceding constructs.</P>
<P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
<TR>
<TD COLSPAN="2"><P CLASS="TableTitle"><A NAME="pgfId=406843"></A>TABLE 10.20 VHDL
binding examples.</TD></TR>
<TR>
<TD><A NAME="pgfId=407091"></A> </TD>
<TD><PRE><B>entity</B> AD2 <B>is</B> <B>port</B> (A1, A2: <B>in</B> BIT; Y: <B>out</B> BIT); <B>end</B>;
<B>architecture</B> B <B>of</B> AD2 <B>is begin</B> Y <= A1 <B>and</B> A2; <B>end</B>;
<B>entity</B> XR2 <B>is port</B> (X1, X2: <B>in</B> BIT; Y: <B>out</B> BIT); <B>end</B>;
<B>architecture</B> B <B>of</B> XR2 <B>is begin</B> Y <= X1 <B>xor </B>X2; <B>end</B>;</PRE>
</TD></TR>
<TR>
<TD><PRE><A NAME="pgfId=406851"></A>
<A NAME="pgfId=407104"></A>
<A NAME="pgfId=406988"></A>component
<A NAME="pgfId=406852"></A>declaration
<A NAME="pgfId=406983"></A> configuration
<A NAME="pgfId=406981"></A> specification
<A NAME="pgfId=406853"></A> </PRE>
</TD>
<TD><PRE><B>entity</B> Half_Adder <B>is port</B> (X, Y: BIT; Sum, Cout: <B>out</B> BIT); <B>end</B>;
<B>architecture</B> Netlist <B>of</B> Half_Adder <B>is use</B> work.<B>all</B>;
<B>component</B> MX <B>port</B> (A, B: BIT; Z :<B>out</B> BIT);<B>end</B> <B>component</B>;
<B>component</B> MA <B>port</B> (A, B: BIT; Z :<B>out</B> BIT);<B>end</B> <B>component</B>;
<B>for</B> G1:MX <B>use entity</B> XR2(B)<B> port</B> <B>map</B>(X1 => A,X2 => B,Y => Z);
<B>begin</B>
G1:MX <B>port</B> <B>map</B>(X, Y, Sum); G2:MA <B>port</B> <B>map</B>(X, Y, Cout);
<B>end</B>;</PRE>
</TD></TR>
<TR>
<TD><PRE><A NAME="pgfId=406869"></A>configuration
<A NAME="pgfId=406870"></A>declaration
<A NAME="pgfId=406872"></A> block
<A NAME="pgfId=406873"></A> configuration
<A NAME="pgfId=406875"></A> component
<A NAME="pgfId=406876"></A> configuration
<A NAME="pgfId=406877"></A> </PRE>
</TD>
<TD><PRE><B>configuration</B> C1 <B>of</B> Half_Adder <B>is</B>
<B>use</B> work.<B>all</B>;
<B>for</B> Netlist
<B>for</B> G2:MA
<B>use</B> <B>entity</B> AD2(B) <B>port</B> <B>map</B>(A1 => A,A2 => B,Y => Z);
<B>end</B> <B>for</B>;
<B>end</B> <B>for</B>;
<B>end</B>;</PRE>
</TD></TR>
</TABLE>
<HR ALIGN="LEFT"><P CLASS="TableFootLast"><SPAN CLASS="footnoteNumber"> 1.</SPAN>
<A NAME="pgfId=426042"></A>Underline means "new to VHDL-93".</P>
<P><HR ALIGN="LEFT"></P>
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