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<TITLE> 10.10 Sequential Statements</TITLE>
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<H2>10.10 Sequential Statements</H2>
<P><A NAME="pgfId=1740"></A>A sequential statement [<A HREF="../../VHDL/LRM/HTML/1076_8.HTM#8">VHDL
LRM8</A>] is defined as follows:</P>
<PRE>sequential_statement ::=
wait_statement | assertion_statement
| signal_assignment_statement
| variable_assignment_statement | procedure_call_statement
| if_statement | case_statement | loop_statement
| next_statement | exit_statement
| return_statement | null_statement <U>| report_statement</U></PRE>
<P><A NAME="pgfId=191444"></A>Sequential statements may only appear in processes
and subprograms. In the following sections I shall describe each of these
different types of sequential statements in turn.</P>
<H3><A NAME="pgfId=3994"></A>10.10.1 Wait Statement</H3>
<P><A NAME="pgfId=30044"></A>The wait statement is central to VHDL, here
are the BNF definitions [<A HREF="../../VHDL/LRM/HTML/1076_8.HTM#8.1">VHDL 93LRM8.1</A>]:</P>
<PRE>wait_statement ::= <U>[label:]</U> <B>wait</B> [sensitivity_clause]
[condition_clause] [timeout_clause] ;
sensitivity_clause ::= <B>on</B> sensitivity_list
sensitivity_list ::= signal_name { , signal_name }
condition_clause ::= <B>until</B> condition
condition ::= boolean_expression
timeout_clause ::= <B>for</B> time_expression</PRE>
<P><A NAME="pgfId=10506"></A>A <TT>wait</TT> statement suspends (stops)
a process or procedure (you cannot use a <TT>wait</TT> statement in a function).
The <TT>wait</TT> statement may be made sensitive to events (changes) on
static signals (the value of the signal must be known at analysis time)
that appear in the sensitivity list after the keyword <TT>on</TT> . These
signals form the sensitivity set of a wait statement. The process will resume
(restart) when an event occurs on any signal (and only signals) in the sensitivity
set. <P CLASS="Body"><A NAME="pgfId=29982"></A>A <TT>wait</TT> statement
may also contain a condition to be met before the process resumes. If there
is no sensitivity clause (there is no keyword <TT>on</TT> ) the sensitivity
set is made from signals (and only signals) from the condition clause that
appears after the keyword <TT>until</TT> (the rules are quite complicated
[<A HREF="../../VHDL/LRM/HTML/1076_8.HTM#8.1">VHDL 93LRM8.1</A>]). <P CLASS="Body"><A NAME="pgfId=29981"></A>Finally a <TT>wait</TT> statement may also contain
a timeout (following the keyword <TT>for</TT> ) after which the process
will resume. Here is the expanded BNF definition, which makes the structure
of the <TT>wait</TT> statement easier to see (but we lose the definitions
of the clauses and the sensitivity list):</P>
<PRE>wait_statement ::= <U>[label:]
</U> <B>wait</B>
[<B>on</B> signal_name {, signal_name}]
[<B>until</B> boolean_expression]
[<B>for</B> time_expression] ;</PRE>
<P><A NAME="pgfId=425331"></A>For example, the statement, <TT>wait on light</TT>
, makes you wait until a traffic light changes (any change). The statement,
<TT>wait until light = green</TT> , makes you wait (even
at a green light) until the traffic signal changes to green. The statement,</P>
<PRE><B>if</B> light = (red <B>or</B> yellow) <B>then</B> <B>wait</B><TT> </TT>
<B>until</B><TT> light = green; </TT>
<B>end</B><TT> </TT>
<B>if</B><TT>;</TT></PRE>
<P><A NAME="pgfId=425401"></A>accurately describes the basic rules at a
traffic intersection. <P CLASS="Body"><A NAME="pgfId=425479"></A>The most
common use of the <TT>wait</TT> statement is to describe synchronous logic,
as in the following model of a D flip-flop:</P>
<PRE><B>entity</B> DFF <B>is</B> <B>port</B> (CLK, D : BIT; Q : <B>out</B> BIT); <B>end</B>;
<B>architecture</B> Behave <B>of</B> DFF <B>is</B>
<B>process</B> <B>begin wait</B><TT> </TT>
<B>until</B><TT> C</TT>
lk = '1'; Q <= D ; <B>end</B> <B>process</B>;
<B>end</B>;</PRE>
<P><A NAME="pgfId=425334"></A>Notice that the statement in line 3 above,
<TT>wait until C</TT> lk = '1', is equivalent to <TT>wait on Clk until C</TT>
lk = '1', and detects a clock edge and not the clock level. Here are some
more complex examples of the use of the <TT>wait</TT> statement:</P>
<PRE><B>entity</B> Wait_1 <B>is</B> <B>port</B> (Clk, s1, s2 :<B>in</B> BIT); <B>end</B>;
<B>architecture</B> Behave <B>of</B> Wait_1 <B>is</B>
<B>signal</B> x : BIT_VECTOR (0 <B>to</B> 15);
<B>begin</B> <B>process</B> <B>variable</B> v : BIT; <B>begin</B>
<B>wait</B>; -- Wait forever, stops simulation.
<B>wait</B> <B>on</B> s1 <B>until</B> s2 = '1'; -- Legal, but s1, s2 are signals so
-- s1 is in sensitivity list, and s2 is not in the sensitivity set.
-- Sensitivity set is s1 and process will not resume at event on s2.
<B>wait</B> <B>on</B> s1, s2; -- resumes at event on signal s1 or s2.
<B>wait</B> <B>on</B> s1 <B>for</B> 10 ns; -- resumes at event on s1 or after 10 ns.
<B>wait</B> <B>on</B> x; -- resumes when any element of array x has an event.
-- wait on x(1 to v); -- Illegal, nonstatic name, since v is a variable.
<B>end</B> <B>process</B>;
<B>end</B>;
<B>entity</B> Wait_2 <B>is</B> <B>port</B> (Clk, s1, s2:<B>in</B> BIT); <B>end</B>;
<B>architecture</B> Behave <B>of</B> Wait_2 <B>is</B>
<B>begin</B> <B>process variable</B> v : BIT; <B>begin</B>
<B>wait</B> <B>on</B> Clk; -- resumes when Clk has an event: rising or falling.
<B>wait</B> <B>until</B> Clk = '1'; -- resumes on rising edge.
<B>wait</B> <B>on</B> Clk <B>until</B> Clk = '1'; -- equivalent to the last statement.
<B>wait</B> <B>on</B> Clk <B>until</B> v = '1';
-- The above is legal, but v is a variable so
-- Clk is in sensitivity list, v is not in the sensitivity set.
-- Sensitivity set is Clk and process will not resume at event on v.
<B>wait</B> <B>on</B> Clk <B>until</B> s1 = '1';
-- The above is legal, but s1 is a signal so
-- Clk is in sensitivity list, s1 is not in the sensitivity set.
-- Sensitivity set is Clk, process will not resume at event on s1.
<B>end</B> <B>process</B>;
<B>end</B>;</PRE>
<P><A NAME="pgfId=362377"></A>You may only use interface signals that may
be read (port modes <TT>in</TT> , <TT>inout</TT> , and <TT>buffer</TT> --see
Section 10.7) in the sensitivity list of a <TT>wait</TT> statement.</P>
<H3><A NAME="pgfId=1788"></A>10.10.2 Assertion and Report Statements</H3>
<P><A NAME="pgfId=10507"></A>You can use an assertion statement to conditionally
issue warnings. The report statement (VHDL-93 only) prints an expression
and is useful for debugging.</P>
<PRE>assertion_statement ::= <U>[label:]</U> <B>assert</B>
boolean_expression [<B>report</B> expression] [<B>severity</B> expression] ;
report_statement
::= <U>[label:] report expression [severity expression] ;</U></PRE>
<P><A NAME="pgfId=241396"></A>Here is an example of an assertion statement:</P>
<PRE><B>entity</B> Assert_1 <B>is port</B> (I:INTEGER:=0); <B>end</B>;
<B>architecture</B> Behave <B>of</B> Assert_1 <B>is</B>
<B>begin</B> <B>process begin</B>
<B>assert</B> (I > 0) <B>report</B> "I is negative or zero"; <B>wait</B>;
<B>end</B> <B>process</B>;
<B>end</B>;</PRE>
<P><A NAME="pgfId=241369"></A>The expression after the keyword <TT>report</TT>
must be of type <TT>STRING</TT> (the default is <TT>"Assertion violation"</TT>
for the <TT>assertion</TT> statement), and the expression after the keyword
<TT>severity</TT> must be of type <TT>SEVERITY_LEVEL</TT> (default <TT>ERROR</TT>
for the <TT>assertion</TT> statement, and <TT>NOTE</TT> for the <TT>report</TT>
statement) defined in the <TT>STANDARD</TT> package. The assertion statement
prints if the assertion condition (after the keyword <TT>assert</TT> ) is
<TT>FALSE</TT> . Simulation normally halts for severity of <TT>ERROR</TT>
or <TT>FAILURE</TT> (you can normally control this threshold in the simulator).</P>
<H3><A NAME="pgfId=4823"></A>10.10.3 Assignment Statements</H3>
<P><A NAME="pgfId=10508"></A>There are two sorts of VHDL assignment statements:
one for signals and one for variables [<A HREF="../../VHDL/LRM/HTML/1076_8.HTM#8.4">VHDL
93LRM8.4</A>-<A HREF="../../VHDL/LRM/HTML/1076_8.HTM#8.5">8.5</A>]. The difference
is in the timing of the update of the LHS. A variable assignment statement
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