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<PRE>I1 : C <B>port</B> <B>map</B>
(L_1 => A_1, L_2 => A_2, L_3 => A_3, L_4 => A_4); -- locals => actuals</PRE>
<P><P CLASS="TableLeft"><A NAME="pgfId=362251"></A>Example configuration:</P>
<PRE><B>for</B> I1 : C <B>use</B> <B>entity</B> E(Behave) <B>port</B> <B>map</B>
(F_1 => L_1, F_2 => L_2, F_3 => L_3, F_4 => L_4); -- formals => locals</PRE>
</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=362263"></A>Interface object, port <CODE>F</CODE></TD>
<TD><PRE><A NAME="pgfId=362265"></A> F_1</PRE>
</TD>
<TD><PRE><A NAME="pgfId=362267"></A> F_2</PRE>
</TD>
<TD><PRE><A NAME="pgfId=362269"></A> F_3</PRE>
</TD>
<TD><PRE><A NAME="pgfId=362271"></A> F_4</PRE>
</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=362276"></A>Mode of <CODE>F</CODE></TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=362278"></A><B><CODE>in</CODE></B> (default)</TD>
<TD><B><CODE>out</CODE></B></TD>
<TD><B><CODE>inout</CODE></B></TD>
<TD><B><CODE>buffer</CODE></B></TD></TR>
<TR>
<TD><P><P CLASS="TableLeft"><A NAME="pgfId=362312"></A>Can you read attributes
of <CODE>F</CODE>?</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=362313"></A>[<A HREF="../../VHDL/LRM/HTML/1076_4.HTM#4.3.2">VHDL
LRM4.3.2</A>]</TD>
<TD><P><P CLASS="TableLeft"><A NAME="pgfId=362315"></A>Yes, but not the attributes:</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=362316"></A>'STABLE</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=362317"></A>'QUIET</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=362318"></A>'DELAYED</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=362319"></A>'TRANSACTION</TD>
<TD><P><P CLASS="TableLeft"><A NAME="pgfId=362321"></A>Yes, but not the attributes:</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=362322"></A>'STABLE 'QUIET</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=362323"></A>'DELAYED</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=362324"></A>'TRANSACTION</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=362325"></A>'EVENT 'ACTIVE</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=362326"></A>'LAST_EVENT</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=362327"></A>'LAST_ACTIVE</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=362328"></A>'LAST_VALUE</TD>
<TD><P><P CLASS="TableLeft"><A NAME="pgfId=362330"></A>Yes, but not the attributes:</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=362331"></A>'STABLE</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=362332"></A>'QUIET</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=362333"></A>'DELAYED</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=362334"></A>'TRANSACTION</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=362336"></A>Yes</TD></TR>
</TABLE>
<P CLASS="Body"><A NAME="pgfId=364087"></A>Table 10.10 lists the restrictions
on reading and updating interface objects including interface signals that
form ports. Table 10.11 lists additional special rules for reading
and updating the attributes of interface signals.</P>
<P><P CLASS="Body"><A NAME="pgfId=363936"></A>There is one more set of rules
that apply to port connections [<A HREF="../../VHDL/LRM/HTML/1076_1.HTM#1.1.1.2">VHDL
LRM 1.1.1.2</A>]. If design entity <CODE>E2</CODE> contains an instance,
<CODE>I1</CODE> , of design entity <CODE>E1</CODE> , then the formals (of
design entity <CODE>E1</CODE> ) are associated with actuals (of instance
<CODE>I1</CODE> ). The actuals (of instance <CODE>I1</CODE> ) are themselves
formal ports (of design entity <CODE>E2</CODE> ). The restrictions illustrated
in Table 10.12 apply to the modes of the port connections from <CODE>E1</CODE>
to <CODE>E2 </CODE>(looking from the inside to the outside).</P>
<P><P CLASS="Body"><A NAME="pgfId=364068"></A>Notice that the allowed connections
diagrammed in Table 10.12 (looking from inside to the outside) are
a superset of those of Table 10.10 (looking from the outside to the
inside). Only the seven types of connections shown in Table 10.12 are
allowed between the ports of nested design entities. The additional rule
that ports of mode <CODE>buffer</CODE> may only have one source, together
with the restrictions on port mode interconnections, limits the use of ports
of mode <CODE>buffer</CODE> .</P>
<P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
<TR>
<TD COLSPAN="5"><P CLASS="TableTitle"><A NAME="pgfId=363943"></A>TABLE 10.12 Connection
rules for port modes.</TD></TR>
<TR>
<TD COLSPAN="5"><PRE><A NAME="pgfId=363953"></A> <B>entity </B>E1 <B>is</B> <B>port</B> (Inside : <B>in </B>BIT);<B> end</B>; <B>architecture</B> Behave <B>of</B> E1 <B>is</B> <B>begin</B> <B>end</B>;
<B>entity </B>E2 <B>is</B> <B>port</B> (Outside : <B>inout </B>BIT := '1');<B> end</B>; <B>architecture </B>Behave <B>of</B> E2 <B>is</B>
<B>component</B> E1 <B>port</B> (Inside : <B>in </B>BIT); <B>end</B> <B>component</B>; <B>begin </B>
I1 : E1 <B>port</B> <B>map</B> (Inside => Outside); -- formal/local (mode in) => actual (mode inout)
<B>end</B>;</PRE>
</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=363967"></A>Possible modes of interface
object, <CODE>Inside</CODE></TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=363969"></A><B><CODE>in</CODE></B> (default)</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=363971"></A><B><CODE>out</CODE></B></TD>
<TD><A NAME="pgfId=363973"></A><B><CODE>inout</CODE></B></TD>
<TD><A NAME="pgfId=363975"></A><B><CODE>buffer</CODE></B></TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=363977"></A>Modes of <CODE>Outside</CODE>
that <CODE>Inside</CODE> may connect to (see below)</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=363979"></A><B><CODE>in</CODE></B> <B><CODE>inout</CODE></B> <B><CODE>buffer</CODE></B></TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=363981"></A><B><CODE>out</CODE></B> <B><CODE>inout</CODE></B></TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=363986"></A><B><CODE>inout</CODE></B>
<A HREF="#pgfId=363985" CLASS="footnote">2</A></TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=363991"></A><B><CODE>buffer</CODE></B>
<A HREF="#pgfId=363990" CLASS="footnote">3</A></TD></TR>
<TR>
<TD COLSPAN="5"><P><P CLASS="TableLeft"><A NAME="pgfId=537704"></A> </P>
<P><IMG SRC="CH10-13.gif" WIDTH="446" HEIGHT="150" NATURALSIZEFLAG="3" ALIGN="BOTTOM"></TD></TR>
</TABLE>
</P>
<H3><A NAME="pgfId=15982"></A>10.7.2 Generics</H3>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=17053"></A>Ports are signals
that carry changing information between entities. A generic is similar to
a port, except generics carry constant, static information [<A HREF="../../VHDL/LRM/HTML/1076_1.HTM#1.1.1.1">VHDL
LRM1.1.1.1</A>]. A generic is an interface constant that, unlike normal
VHDL constants, may be given a value in a component instantiation statement
or in a configuration specification. You declare generics in an entity declaration
and you use generics in a similar fashion to ports. The following example
uses a generic parameter to alter the size of a gate:</P>
<PRE><B>entity</B> AndGateNWide <B>is </B>
<B> generic </B>(N : NATURAL := 2);
<B>port</B> (Inputs : BIT_VECTOR(1 <B>to</B> N); Result : <B>out</B> BIT);
<B>end</B>;</PRE>
<P><P CLASS="Body"><A NAME="pgfId=16018"></A>Notice that the generic interface
list precedes the port interface list. Generics are useful to carry timing
(delay) information, as in the next example:</P>
<PRE><B>entity</B> AndT <B>is </B>
<B> generic </B>(TPD : TIME := 1 ns);
<B> port </B>(a, b : BIT := '0'; q: <B>out</B> BIT);
<B>end</B>;
<B>architecture</B> Behave <B>of</B> AndT <B>is </B>
<B> begin</B> q <= a <B>and</B> b <B>after</B> TPD;
<B>end</B>;
<B>entity</B> AndT_Test_1 <B>is</B> <B>end</B>;
<B>architecture</B> Netlist_1 <B>of</B> AndT_Test_1 <B>is</B>
<B> component</B> MyAnd
<B> port </B>(a, b : BIT; q : <B>out</B> BIT);
<B> end</B> <B>component</B>;
<B> signal</B> a1, b1, q1 : BIT := '1';
<B> begin</B>
And1 : MyAnd <B>port</B> <B>map</B> (a1, b1, q1);
<B>end</B> Netlist_1;
<B>configuration</B> Simplest_1 <B>of</B> AndT_Test_1 <B>is</B> <B>use</B> work.<B>all</B>;
<B>for</B> Netlist_1 <B>for</B> And1 : MyAnd
<B>use</B> <B>entity</B> AndT(Behave) <B>generic</B> <B>map</B> (2 ns);
<B>end</B> <B>for</B>; <B>end</B> <B>for</B>;
<B>end </B>Simplest_1;</PRE>
<P><P CLASS="Body"><A NAME="pgfId=257117"></A>The configuration declaration,
<CODE>Simplest_1</CODE>, changes the default delay (equal to 1 ns, declared
as a default expression in the entity) to 2 ns. Techniques based on this
method are useful in ASIC design. Prelayout simulation uses the default
timing values. Back-annotation alters the delay in the configuration for
postlayout simulation. When we change the delay we only need to reanalyze
the configuration, not the rest of the ASIC model.</P>
<P><P CLASS="Body"><A NAME="pgfId=257119"></A>There was initially no standard
in VHDL for how timing generics should be used, and the lack of a standard
was a major problem for ASIC designers. The IEEE 1076.4 VITAL standard addresses
this problem (see Section 13.5.5).</P>
<P><HR ALIGN="LEFT"><P CLASS="TableFootLast"><SPAN CLASS="footnoteNumber">
1.</SPAN> <A NAME="pgfId=363832"></A>There are additional rules for interface
objects that are signals (ports)--see Tables 10.11 and 10.12.</P>
<P><P CLASS="TableFootnote"><SPAN CLASS="footnoteNumber"> 2.</SPAN> <A NAME="pgfId=363985"></A>A signal of mode inout can be updated by any number
of sources [VHDL 87LRM4.3.3, <A HREF="../../VHDL/LRM/HTML/1076_4.HTM#4.3.2">93LRM4.3.2</A>].</P>
<P><P CLASS="TableFootLast"><SPAN CLASS="footnoteNumber"> 3.</SPAN> <A NAME="pgfId=363990"></A>A signal of mode buffer can be updated by at most
one source [<A HREF="../../VHDL/LRM/HTML/1076_1.HTM#1.1.1.2">VHDL LRM1.1.1.2</A>].</P>
<P><HR ALIGN="LEFT"></P>
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