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<H2>10.7 Interface Declarations</H2>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=16881"></A>An interface declaration
declares interface objects that may be interface constants, signals, variables,
or files [VHDL 87LRM4.3.3, <A HREF="../../VHDL/LRM/HTML/1076_4.HTM#4.3.2">93LRM4.3.2</A>].
Interface constants are generics of a design entity, a component, or a block,
or parameters of subprograms. Interface signals are ports of a design entity,
component, or block, and parameters of subprograms. Interface variables
and interface files are parameters of subprograms.</P>
<P><P CLASS="Body"><A NAME="pgfId=363022"></A>Each interface object has
a mode that indicates the direction of information flow. The most common
modes are <CODE>in</CODE> (the default), <CODE>out</CODE> , <CODE>inout</CODE>
, and <CODE>buffer</CODE> (a fifth mode, <CODE>linkage</CODE> , is used
to communicate with other languages and is infrequently used in ASIC design).
The restrictions on the use of objects with these modes are listed in Table 10.10.
An interface object is read when you use it on the RHS of an assignment
statement, for example, or when the object is associated with another interface
object of modes <CODE>in</CODE> , <CODE>inout</CODE> (or <CODE>linkage</CODE>
). An interface object is updated when you use it on the LHS side of an
assignment statement or when the object is associated with another interface
object of mode <CODE>out</CODE> , <CODE>buffer</CODE> , <CODE>inout</CODE>
(or <CODE>linkage</CODE> ). The restrictions on reading and updating objects
generate the diagram at the bottom of Table 10.10 that shows the 10
allowed types of interconnections (these rules for modes <CODE>buffer</CODE>
and <CODE>inout</CODE> are the same). The interface objects (<CODE> Inside</CODE>
and <CODE>Outside</CODE> ) in the example in this table are ports (and thus
interface signals), but remember that interface objects may also be interface
constants, variables, and files.</P>
<P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
<TR>
<TD COLSPAN="5"><P CLASS="TableTitle"><A NAME="pgfId=362675"></A>TABLE 10.10 Modes
of interface objects and their properties.</TD></TR>
<TR>
<TD COLSPAN="5"><PRE><B>entity </B>E1 <B>is</B> <B>port</B> (Inside : <B>in </B>BIT);<B> end</B>; <B>architecture</B> Behave <B>of</B> E1 <B>is</B> <B>begin</B> <B>end</B>;
<B>entity </B>E2 <B>is</B> <B>port</B> (Outside : <B>inout </B>BIT := '1');<B> end</B>; <B>architecture </B>Behave <B>of</B> E2 <B>is</B>
<B>component</B> E1 <B>port</B> (Inside: <B>in </B>BIT); <B>end</B> <B>component</B>; <B>signal </B>UpdateMe : BIT; <B>begin </B>
I1 : E1 <B>port</B> <B>map</B> (Inside => Outside); -- formal/local (mode in) => actual (mode inout)
UpdateMe <= Outside; -- OK to read Outside (mode inout)
Outside <= '0' <B>after</B> 10 ns; -- and OK to update Outside (mode inout)
<B>end</B>;</PRE>
</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=362716"></A>Possible modes of interface
object, <CODE>Outside</CODE></TD>
<TD><B><CODE>in</CODE></B> (default)</TD>
<TD><B><CODE>out</CODE></B></TD>
<TD><B><CODE>inout</CODE></B></TD>
<TD><B><CODE>buffer</CODE></B></TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=362726"></A>Can you read <CODE>Outside</CODE>
(RHS of assignment)?</TD>
<TD>Yes</TD>
<TD>No</TD>
<TD>Yes</TD>
<TD>Yes</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=362736"></A>Can you update <CODE>Outside</CODE>
(LHS of assignment)?</TD>
<TD>No</TD>
<TD>Yes</TD>
<TD>Yes</TD>
<TD>Yes</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=362746"></A>Modes of <CODE>Inside</CODE>
that <CODE>Outside</CODE> may connect to (see below) <A HREF="#pgfId=363832" CLASS="footnote">1</A></TD>
<TD><B><CODE>in</CODE></B></TD>
<TD><B><CODE>out</CODE></B></TD>
<TD>any</TD>
<TD>any</TD></TR>
<TR>
<TD COLSPAN="5"><P><P CLASS="TableLeft"><A NAME="pgfId=363058"></A> </P>
<P><IMG SRC="CH10-12.gif" WIDTH="410" HEIGHT="150" NATURALSIZEFLAG="3" ALIGN="BOTTOM"></TD></TR>
</TABLE>
<P CLASS="Body"><A NAME="pgfId=363546"></A>There are other special-case
rules for reading and updating interface signals, constants, variables,
and files that I shall cover in the following sections. The situation is
like the spelling rule, "i before e except after c." Table 10.10
corresponds to the rule "i before e."</P>
<H3><A NAME="pgfId=113831"></A>10.7.1 Port Declaration</H3>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=113833"></A>Interface objects
that are signals are called ports [<A HREF="../../VHDL/LRM/HTML/1076_1.HTM#1.1.1.2">VHDL
93LRM1.1.1.2</A>]. You may think of ports as "connectors" and
you must declare them as follows:</P>
<PRE><B>port</B> (<I>port_</I>interface_list)
interface_list ::=
<I>port_</I>interface_declaration {; <I>port_</I>interface_declaration}</PRE>
<P><P CLASS="Body"><A NAME="pgfId=10980"></A>A port interface declaration
is a list of ports that are the inputs and outputs of an entity, a block,
or a component declaration:</P>
<PRE>interface_declaration ::=
[<B>signal</B>]
identifier {, identifier}:[<B>in</B>|<B>out</B>|<B>inout</B>|<B>buffer</B>|<B>linkage</B>]
subtype_indication [<B>bus</B>] [:= <I>static_</I>expression]</PRE>
<P><P CLASS="Body"><A NAME="pgfId=9984"></A>Each port forms an implicit
signal declaration and has a port mode. I shall discuss <CODE>bus</CODE>
, which is a signal kind, in Section 10.13.1. Here is an example of
an entity declaration that has five ports:</P>
<PRE><B>entity</B> Association_1 <B>is </B>
<B> port</B> (<B>signal</B> X, Y : <B>in</B> BIT := '0'; Z1, Z2, Z3 : <B>out</B> BIT);
<B>end</B>;</PRE>
<P><P CLASS="Body"><A NAME="pgfId=12807"></A>In the preceding declaration
the keyword <CODE>signal</CODE> is redundant (because all ports are signals)
and may be omitted. You may also omit the port mode <CODE>in</CODE> because
it is the default mode. In this example, the input ports <CODE>X</CODE>
and <CODE>Y</CODE> are driven by a default value (in general a default expression)
of <CODE>'0' </CODE>if (and only if ) the ports are left unconnected or
open. If you do leave an input port open, the port must have a default expression.</P>
<P><P CLASS="Body"><A NAME="pgfId=113847"></A>You use a port map and either
positional association or named association to connect the formals of an
entity with the locals of a component. Port maps also associate (connect)
the locals of a component with the actuals of an instance. For an example
of formal, local, and actual ports, and explanation of their function, see
Section 10.5, where we declared an entity <CODE>AndGate</CODE>. The
following example shows how to bind a component to the entity <CODE>AndGate</CODE>
(in this case we use the default binding) and associate the ports. Notice
that if we mix positional and named association then all positional associations
must come first.</P>
<PRE><B>use </B>work<B>.all</B>; -- makes analyzed design entity AndGate(Simple) visible.
<B>architecture</B> Netlist <B>of</B> Association_1 <B>is</B>
-- The formal port clause for entity AndGate looks like this:
<B>-</B>- port (And_in_1, And_in_2: in BIT; And_out : out BIT); -- Formals.
<B>component</B> AndGate <B>port</B>
(And_in_1, And_in_2 : <B>in</B> BIT; And_out : <B>out</B> BIT); -- Locals.
<B>end</B> <B>component</B>;
<B>begin</B>
-- The component and entity have the same names: AndGate.
-- The port names are also the same: And_in_1, And_in_2, And_out,
-- so we can use default binding without a configuration.
-- The last (and only) architecture for AndGate will be used: Simple.
A1:AndGate <B>port</B> <B>map</B> (X, Y, Z1); -- positional association
A2:AndGate <B>port</B> <B>map</B> (And_in_2=>Y, And_out=>Z2, And_in_1=>X); -- named
A3:AndGate <B>port</B> <B>map</B> (X, And_out => Z3, And_in_2 => Y); -- both
<B>end</B>;</PRE>
<P><P CLASS="Body"><A NAME="pgfId=343625"></A>The interface object rules
of Table 10.10 apply to ports. The rule that forbids updating an interface
object of mode <CODE>in</CODE> prevents modifying an input port (by placing
the input signal on the left-hand side of an assignment statement, for example).
Less obviously, you cannot read a port of mode <CODE>out</CODE> (that is
you cannot place an output signal on the right-hand side of an assignment
statement). This stops you from accidentally reading an output signal that
may be connected to a net with multiple drivers. In this case the value
you would read (the unresolved output signal) might not be the same as the
resolved signal value. For example, in the following code, since <CODE>Clock</CODE>
is a port of mode <CODE>out</CODE> , you cannot read <CODE>Clock</CODE>
directly. Instead you can transfer <CODE>Clock</CODE> to an intermediate
variable and read the intermediate variable instead:</P>
<PRE><B>entity</B> ClockGen_1 <B>is</B> <B>port</B> (Clock : <B>out</B> BIT); <B>end</B>;
<B>architecture</B> Behave <B>of</B> ClockGen_1 <B>is</B>
<B>begin process</B> <B>variable</B> Temp : BIT := '1';
<B>begin</B>
-- Clock <= not Clock; -- Illegal, you cannot read Clock (mode out),
Temp := <B>not</B> Temp; -- use a temporary variable instead.
Clock <= Temp <B>after</B> 10 ns; <B>wait</B> <B>for</B> 10 ns;
<B>if</B> (now > 100 ns) <B>then</B> <B>wait</B>; <B>end</B> <B>if</B>; <B>end</B> <B>process</B>;
<B>end</B>;</PRE>
<P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
<TR>
<TD COLSPAN="5"><P CLASS="TableTitle"><A NAME="pgfId=362233"></A>TABLE 10.11 Properties
of ports.</TD></TR>
<TR>
<TD COLSPAN="5"><P><P CLASS="TableLeft"><A NAME="pgfId=362243"></A>Example entity declaration:</P>
<PRE><B>entity</B> E <B>is port</B> (F_1:BIT; F_2:<B>out</B> BIT; F_3:<B>inout</B> BIT; F_4:<B>buffer</B> BIT); <B>end</B>; -- formals</PRE>
<P><P CLASS="TableLeft"><A NAME="pgfId=537697"></A>Example component declaration:</P>
<PRE><B>component</B> C <B>port</B> (L_1:BIT; L_2:<B>out</B> BIT; L_3:<B>inout</B> BIT; L_4:<B>buffer</B> BIT); -- locals
<B>end</B> <B>component</B>;</PRE>
<P><P CLASS="TableLeft"><A NAME="pgfId=362248"></A>Example component instantiation:</P>
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