ch11.02.htm
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VideoRam[2] is 00000000000000000000000000000001
VideoRam[7] is xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxz</PRE>
<P><P CLASS="Body"><A NAME="pgfId=6567"></A>We may also declare an <B>integer
array</B> or <B>time array</B> in the same way as an array of <CODE>reg</CODE>
, but there are no real arrays [<A HREF="../../Verilog/LRM/HTML/03/ch03.9.htm">Verilog
LRM 3.9</A>]:</P>
<PRE><A HREF="../../Code/cd11b.htm#anchor26565656"><IMG SRC="../../Images/HDL.gif" WIDTH="32" HEIGHT="32" ALIGN="BOTTOM" NATURALSIZEFLAG="3"></A>
<B>module</B> declarations_6;
<B>integer</B> Number [1:100]; // Notice that size follows name
<B>time</B> Time_Log [1:1000]; // - as in an array of reg.
// real Illegal [1:10]; // Illegal. There are no real arrays.
<B>endmodule</B></PRE>
<H2><A NAME="pgfId=9859"></A>11.2.3 Other Wire Types</H2>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=9860"></A>There are the following
other Verilog wire types (rarely used in ASIC design) [<A HREF="../../Verilog/LRM/HTML/03/ch03.7.htm">Verilog
LRM 3.7</A>]:</P>
<UL>
<LI><A NAME="pgfId=9864"></A><CODE>wand</CODE> , <CODE>wor</CODE> , <CODE>triand</CODE>
, and <CODE>trior </CODE>model wired logic. Wiring, or dotting, the outputs
of two gates generates a logic function (in emitter-coupled logic, ECL,
or in an EPROM, for example). This is one area in which the logic values
<CODE>'z'</CODE> and <CODE>'x'</CODE> are treated differently.
<LI><A NAME="pgfId=9865"></A><CODE>tri0</CODE> and <CODE>tri1 </CODE>model
resistive connections to VSS or VDD.
<LI><A NAME="pgfId=9869"></A><CODE>trireg </CODE>is like a <CODE>wire</CODE>
but associates some capacitance with the net, so it can model charge storage.
</UL>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=42698"></A>There are also other
keywords that may appear in declarations:</P>
<UL>
<LI><A NAME="pgfId=42703"></A><CODE>scalared</CODE> and <CODE>vectored
</CODE>are properties of vectors [<A HREF="../../Verilog/LRM/HTML/03/ch03.3.htm">Verilog
LRM 3.3</A>].
<LI><A NAME="pgfId=42709"></A><CODE>small</CODE> , <CODE>medium</CODE>
, and <CODE>large</CODE> model the charge strength of <CODE>trireg</CODE>
connections [Verilog LRM 7].
</UL>
<H2><A NAME="pgfId=758"></A>11.2.4 Numbers</H2>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=172031"></A><B>Constant numbers</B>
are integer or real constants [<A HREF="../../Verilog/LRM/HTML/02/ch02.5.htm">Verilog
LRM 2.5</A>]. <B>Integer constants</B> are written as</P>
<P><P CLASS="Equation"><A NAME="pgfId=172038"></A><CODE>width'radix value</CODE></P>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=171894"></A>where <CODE>width</CODE>
and <CODE>radix</CODE> are optional. The <B>radix</B> (or base) indicates
the type of number: <B>decimal</B> (<CODE> d</CODE> or <CODE>D</CODE> ),
<B>hex</B> (<CODE> h</CODE> or <CODE>H</CODE> ), <B>octal</B> (<CODE> o</CODE>
or <CODE>O</CODE> ), or <B>binary</B> (<CODE> b</CODE> or <CODE>B</CODE>
). A number may be <B>sized</B> or <B>unsized</B>. The length of an unsized
number is implementation dependent. We can use <CODE>'1'</CODE> and <CODE>'0'</CODE>
as numbers since they cannot be identifiers, but we must write<CODE> 1'bx</CODE>
and <CODE>1'bz</CODE> for <CODE>'x'</CODE> and <CODE>'z'</CODE> . A number
may be declared as a <B>parameter</B> [<A HREF="../../Verilog/LRM/HTML/03/ch03.a.htm">Verilog
LRM 3.10</A>]. A parameter assignment belongs inside a module declaration
and has <B>local scope</B> [<A HREF="../../Verilog/LRM/HTML/03/ch03.9.htm">Verilog
LRM3.11</A>]. <B>Real constants</B> are written using decimal (100.0) or
scientific notation (1e2) and follow IEEE Std 754-1985 for double-precision
floating-point numbers. Reals are rounded to the nearest integer, ties (numbers
that end in .5) round away from zero [<A HREF="../../Verilog/LRM/HTML/03/ch03.9.htm">Verilog
LRM 3.9</A>], but not all implementations follow this rule (the output from
the following code is from VeriWell, which rounds ties toward zero for negative
integers).</P>
<PRE><A HREF="../../Code/cd11b.htm#anchor26567015"><IMG SRC="../../Images/HDL.gif" WIDTH="32" HEIGHT="32" ALIGN="BOTTOM" NATURALSIZEFLAG="3"></A>
<B>module</B> constants;
<B>parameter</B> H12_UNSIZED = 'h 12; // Unsized hex 12 = decimal 18.
<B>parameter</B> H12_SIZED = 6'h 12; // Sized hex 12 = decimal 18.
// Note: a space between base and value is OK.
// Note: `' (single apostrophes) are not the same as the ' character.
<B>parameter</B> D42 = 8'B0010_1010; // bin 101010 = dec 42
// OK to use underscores to increase readability.
<B>parameter</B> D123 = 123; // Unsized decimal (the default).
<B>parameter</B> D63 = 8'o 77; // Sized octal, decimal 63.
// parameter ILLEGAL = 1'o9; // No 9's in octal numbers!
// A = 'hx and B = 'ox assume a 32 bit width.
<B>parameter</B> A = 'h x, B = 'o x, C = 8'b x, D = 'h z, E = 16'h ????;
// Note the use of ? instead of z, 16'h ???? is the same as 16'h zzzz.
// Also note the automatic extension to a width of 16 bits.
<B>reg</B> [3:0] B0011,Bxxx1,Bzzz1; <B>real</B> R1,R2,R3; <B>integer</B> I1,I3,I_3;
<B>parameter</B> BXZ = 8'b1x0x1z0z;
<B>initial</B> <B>begin</B>
B0011 = 4'b11; Bxxx1 = 4'bx1; Bzzz1 = 4'bz1; // Left padded.
R1 = 0.1e1; R2 = 2.0; R3 = 30E-01; // Real numbers.
I1 = 1.1; I3 = 2.5; I_3 = -2.5; // IEEE rounds away from 0.
<B>end initial</B> <B>begin</B> #1;
$display
("H12_UNSIZED, H12_SIZED (hex) = %h, %h",H12_UNSIZED, H12_SIZED);
$display("D42 (bin) = %b",D42," (dec) = %d",D42);
$display("D123 (hex) = %h",D123," (dec) = %d",D123);
$display("D63 (oct) = %o",D63);
$display("A (hex) = %h",A," B (hex) = %h",B);
$display("C (hex) = %h",C," D (hex) = %h",D," E (hex) = %h",E);
$display("BXZ (bin) = %b",BXZ," (hex) = %h",BXZ);
$display("B0011, Bxxx1, Bzzz1 (bin) = %b, %b, %b",B0011,Bxxx1,Bzzz1);
$display("R1, R2, R3 (e, f, g) = %e, %f, %g", R1, R2, R3);
$display("I1, I3, I_3 (d) = %d, %d, %d", I1, I3, I_3);
<B>end</B>
<B>endmodule</B>
H12_UNSIZED, H12_SIZED (hex) = 00000012, 12
D42 (bin) = 00101010 (dec) = 42
D123 (hex) = 0000007b (dec) = 123
D63 (oct) = 077
A (hex) = xxxxxxxx B (hex) = xxxxxxxx
C (hex) = xx D (hex) = zzzzzzzz E (hex) = zzzz
BXZ (bin) = 1x0x1z0z (hex) = XZ
B0011, Bxxx1, Bzzz1 (bin) = 0011, xxx1, zzz1
R1, R2, R3 (e, f, g) = 1.000000e+00, 2.000000, 3
I1, I3, I_3 (d) = 1, 3, -2</PRE>
<H2><A NAME="pgfId=166691"></A>11.2.5 Negative Numbers</H2>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=172632"></A>Integer numbers are
<B>signed</B> (two's complement) or <B>unsigned</B>. The following example
illustrates the handling of negative constants [Verilog LRM <A HREF="../../Verilog/LRM/HTML/03/ch03.2.htm">3.2</A>
, <A HREF="../../Verilog/LRM/HTML/04/ch04.1.htm">4.1</A>]:</P>
<PRE>
<A HREF="../../Code/cd11b.htm#anchor26568916"><IMG SRC="../../Images/HDL.gif" WIDTH="32" HEIGHT="32" ALIGN="BOTTOM" NATURALSIZEFLAG="3"></A>
<B>module</B> negative_numbers;
<B>parameter</B> PA = -12, PB = -'d12, PC = -32'd12, PD = -4'd12;
<B>integer</B> IA , IB , IC , ID ; <B>reg</B> [31:0] RA , RB , RC , RD ;
<B>initial</B> <B>begin</B> #1;
IA = -12; IB = -'d12; IC = -32'd12; ID = -4'd12;
RA = -12; RB = -'d12; RC = -32'd12; RD = -4'd12; #1;
$display(" parameter integer reg[31:0]");
$display ("-12 =",PA,IA,,,RA);
$displayh(" ",,,,PA,,,,IA,,,,,RA);
$display ("-'d12 =",,PB,IB,,,RB);
$displayh(" ",,,,PB,,,,IB,,,,,RB);
$display ("-32'd12 =",,PC,IC,,,RC);
$displayh(" ",,,,PC,,,,IC,,,,,RC);
$display ("-4'd12 =",,,,,,,,,,PD,ID,,,RD);
$displayh(" ",,,,,,,,,,,PD,,,,ID,,,,,RD);
<B>end</B>
<B>endmodule</B>
parameter integer reg[31:0]
-12 = -12 -12 4294967284
fffffff4 fffffff4 fffffff4
-'d12 = 4294967284 -12 4294967284
fffffff4 fffffff4 fffffff4
-32'd12 = 4294967284 -12 4294967284
fffffff4 fffffff4 fffffff4
-4'd12 = 4 -12 4294967284
4 fffffff4 fffffff4</PRE>
<P><P CLASS="Body"><A NAME="pgfId=174904"></A>Verilog only "keeps track"
of the sign of a negative constant if it is (1) assigned to an <CODE>integer</CODE>
or (2) assigned to a <CODE>parameter</CODE> without using a base (essentially
the same thing). In other cases (even though the bit representations may
be identical to the signed number--hexadecimal <CODE>fffffff4</CODE> in
the previous example), a negative constant is treated as an unsigned number.
Once Verilog "loses" the sign, keeping track of signed numbers
becomes your responsibility (see also Section 11.3.1).</P>
<H2><A NAME="pgfId=174565"></A>11.2.6 Strings</H2>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=71574"></A>The code listings
in this book use <CODE>Courier</CODE> font. The ISO/ANSI standard for the
ASCII code defines the characters, but not the appearance of the graphic
symbol in any particular font. The confusing characters are the quote and
accent characters:</P>
<PRE><A HREF="../../Code/cd11b.htm#anchor26570889"><IMG SRC="../../Images/HDL.gif" WIDTH="32" HEIGHT="32" ALIGN="BOTTOM" NATURALSIZEFLAG="3"></A>
<B>module</B> characters; /*
" is ASCII 34 (hex 22), double quote.
' is ASCII 39 (hex 27), tick or apostrophe.
/ is ASCII 47 (hex 2F), forward slash.
\ is ASCII 92 (hex 5C), back slash.
` is ASCII 96 (hex 60), accent grave.
| is ASCII 124 (hex 7C), vertical bar.
There are no standards for the graphic symbols for codes above 128.
´ is 171 (hex AB), accent acute in almost all fonts.
" is 210 (hex D2), open double quote, like 66 (in some fonts).
" is 211 (hex D3), close double quote, like 99 (in some fonts).
` is 212 (hex D4), open single quote, like 6 (in some fonts).
' is 213 (hex D5), close single quote, like 9 (in some fonts).
*/ <B>endmodule</B></PRE>
<P><P CLASS="Body"><A NAME="pgfId=57710"></A>Here is an example showing
the use of <B>string constants</B> [<A HREF="../../Verilog/LRM/HTML/02/ch02.6.htm">Verilog
LRM 2.6</A>]:</P>
<PRE><A HREF="../../Code/cd11b.htm#anchor26573144"><IMG SRC="../../Images/HDL.gif" WIDTH="32" HEIGHT="32" ALIGN="BOTTOM" NATURALSIZEFLAG="3"></A>
<B>module</B> text;
<B>parameter</B> A_String = "abc"; // string constant, must be on one line
<B>parameter</B> Say = "Say \"Hey!\"";
// use escape quote \" for an embedded quote
<B>parameter</B> Tab = "\t"; // tab character
<B>parameter</B> NewLine = "\n"; // newline character
<B>parameter</B> BackSlash = "\\"; // back slash
<B>parameter</B> Tick = "\047"; // ASCII code for tick in octal
// parameter Illegal = "\500"; // illegal - no such ASCII code
<B>initial</B> <B>begin</B>$display("A_String(str) = %s ",A_String," (hex) = %h ",A_String);
$display("Say = %s ",Say," Say \"Hey!\"");
$display("NewLine(str) = %s ",NewLine," (hex) = %h ",NewLine);
$display("\\(str) = %s ",BackSlash," (hex) = %h ",BackSlash);
$display("Tab(str) = %s ",Tab," (hex) = %h ",Tab,"1 newline...");
$display("\n");
$display("Tick(str) = %s ",Tick," (hex) = %h ",Tick);
#1.23; $display("Time is %t", $time);
<B>end</B>
<B>endmodule</B>
A_String(str) = abc (hex) = 616263
Say = Say \"Hey!\" Say "Hey!"
NewLine(str) = \n (hex) = 0a
\(str) = \\ (hex) = 5c
Tab(str) = \t (hex) = 09 1 newline...
Tick(str) = ' (hex) = 27
Time is 1</PRE>
<P><P CLASS="Body"><A NAME="pgfId=37484"></A>Instead of parameters you may
use a <B>define directive</B> that is a <B>compiler directive</B>, and not
a statement [Verilog LRM 16]. The <CODE>define</CODE> directive has
<B>global scope</B>:</P>
<PRE><A HREF="../../Code/cd11b.htm#anchor26576005"><IMG SRC="../../Images/HDL.gif" WIDTH="32" HEIGHT="32" ALIGN="BOTTOM" NATURALSIZEFLAG="3"></A>
<B>module</B> define;
define G_BUSWIDTH 32 // Bus width parameter (G_ for global).
/* Note: there is no semicolon at end of a compiler directive. The character ` is ASCII 96 (hex 60), accent grave, it slopes down from left to right. It is not the tick or apostrophe character ' (ASCII 39 or hex 27)*/
<B>wire</B> [`G_BUSWIDTH:0]MyBus; // A 32-bit bus.
<B>endmodule</B></PRE>
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