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<H1>11.9 Logic-Gate Modeling</H1>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=9999"></A>Verilog has a set of
built-in logic models and you may also define your own models.</P>
<H2><A NAME="pgfId=5204"></A>11.9.1 Built-in Logic Models</H2>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=201039"></A>Verilog's built-in
logic models are the following <B>primitives</B> [Verilog LRM7]:</P>
<UL>
<LI><A NAME="pgfId=201040"></A><CODE>and, nand, nor, or, xor, xnor </CODE>
</UL>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=201041"></A>You may use these
primitives as you use modules. For example:</P>
<PRE>
<B>module</B> primitive;
<B>nand</B> (strong0, strong1) #2.2
Nand_1(n001, n004, n005),
Nand_2(n003, n001, n005, n002);
<B>nand</B> (n006, n005, n002);
<B>endmodule</B></PRE>
<P><P CLASS="Body"><A NAME="pgfId=5221"></A>This module models three NAND
gates (<A HREF="#pgfId=22483">Figure 11.2</A>). The first gate (line
3) is a two-input gate named <CODE>Nand_1</CODE> ; the second gate (line
4) is a three-input gate named<CODE> Nand_2</CODE> ; the third gate (line
5) is unnamed. The first two gates have strong drive strengths [Verilog
LRM3.4] (these are the defaults anyway) and 2.2 ns delay; the third
gate takes the default values for drive strength (strong) and delay (zero).
The first port of a primitive gate is always the output port. The remaining
ports for a primitive gate (any number of them) are the input ports.</P>
<P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
<TR>
<TD><P CLASS="TableFigure"><A NAME="pgfId=20016"></A><IMG SRC="CH11-2.gif" ALIGN="BASELINE" WIDTH="313" HEIGHT="140" NATURALSIZEFLAG="3"> </TD></TR>
<TR>
<TD><P CLASS="TableFigureTitle"><A NAME="pgfId=22483"></A>FIGURE 11.2 An
example schematic (drawn with Capilano's DesignWorks) to illustrate the
use of Verilog primitive gates.</TD></TR>
</TABLE>
<P CLASS="Body"><A NAME="pgfId=5360"></A><A HREF="#pgfId=5277">Table 11.5</A>
shows the definition of the <CODE>and</CODE> gate primitive (I use lowercase<CODE>
'and'</CODE> as the name of the Verilog primitive, rather than <CODE>'AND'</CODE>
, since Verilog is case-sensitive). Notice that if one input to the primitive
<CODE>'and'</CODE> gate is zero, the output is zero, no matter what the
other input is.</P>
<P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
<TR>
<TD COLSPAN="5"><P CLASS="TableTitle"><A NAME="pgfId=5277"></A>TABLE 11.5 Definition
of the Verilog primitive 'and' gate.</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=5224"></A>'and'</TD>
<TD><P CLASS="Table"><A NAME="pgfId=5226"></A>0</TD>
<TD><P CLASS="Table"><A NAME="pgfId=5228"></A>1</TD>
<TD><P CLASS="Table"><A NAME="pgfId=5230"></A>x</TD>
<TD><P CLASS="Table"><A NAME="pgfId=5232"></A>z</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=5234"></A>0</TD>
<TD><P CLASS="Table"><A NAME="pgfId=5236"></A>0</TD>
<TD><P CLASS="Table"><A NAME="pgfId=5238"></A>0</TD>
<TD><P CLASS="Table"><A NAME="pgfId=5240"></A>0</TD>
<TD><P CLASS="Table"><A NAME="pgfId=5242"></A>0</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=5244"></A>1</TD>
<TD><P CLASS="Table"><A NAME="pgfId=5246"></A>0</TD>
<TD><P CLASS="Table"><A NAME="pgfId=5248"></A>1</TD>
<TD><P CLASS="Table"><A NAME="pgfId=5250"></A>x</TD>
<TD><P CLASS="Table"><A NAME="pgfId=5252"></A>x</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=5254"></A>x</TD>
<TD><P CLASS="Table"><A NAME="pgfId=5256"></A>0</TD>
<TD><P CLASS="Table"><A NAME="pgfId=5258"></A>x</TD>
<TD><P CLASS="Table"><A NAME="pgfId=5260"></A>x</TD>
<TD><P CLASS="Table"><A NAME="pgfId=5262"></A>x</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=5264"></A>z</TD>
<TD><P CLASS="Table"><A NAME="pgfId=5266"></A>0</TD>
<TD><P CLASS="Table"><A NAME="pgfId=5268"></A>x</TD>
<TD><P CLASS="Table"><A NAME="pgfId=5270"></A>x</TD>
<TD><P CLASS="Table"><A NAME="pgfId=5272"></A>x</TD></TR>
</TABLE>
</P>
<H2><A NAME="pgfId=5368"></A>11.9.2 User-Defined Primitives</H2>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=6285"></A>We can define primitive
gates (a <B>user-defined primitive</B> or<B> UDP</B>) using a truth-table
specification [Verilog LRM8]. The first port of a UDP must be an <CODE>output</CODE>
port, and this must be the only o<CODE> utput</CODE> port (we may
not use vector or <CODE>inout</CODE> ports):</P>
<PRE>
<B>primitive</B> Adder(Sum, InA, InB);
<B>output</B> Sum; <B>input</B> Ina, InB;
<B>table </B>
// inputs : output
00 : 0;
01 : 1;
10 : 1;
11 : 0;
<B>endtable</B>
<B>endprimitive</B></PRE>
<P><P CLASS="Body"><A NAME="pgfId=5379"></A>We may only specify the values
<CODE>'0'</CODE> , <CODE>'1'</CODE> , and <CODE>'x'</CODE> as inputs in
a <B>UDP truth table</B>. Any<CODE> 'z'</CODE> input is treated as an <CODE>'x'</CODE>
. If there is no entry in a UDP truth table that exactly matches a set of
inputs, the output is <CODE>'x'</CODE> (unknown).</P>
<P><P CLASS="Body"><A NAME="pgfId=6638"></A>We can construct a UDP model
for sequential logic by including a state in the UDP truth-table definition.
The state goes between an input and an output in the table and the output
then represents the next state. The following sequential UDP model also
illustrates the use of shorthand notation in a UDP truth table:</P>
<PRE>
<B>primitive</B> DLatch(Q, Clock, Data);
<B>output</B> Q; <B>reg</B> Q; <B>input</B> Clock, Data;
<B>table </B>
//inputs : present state : output (next state)
1 0 : ? : 0; // ? represents 0,1, or x (input or present state).
1 1 : b : 1; // b represents 0 or 1 (input or present state).
1 1 : x : 1; // Could have combined this with previous line.
0 ? : ? : -; // - represents no change in an output.
<B>endtable</B>
<B>endprimitive</B></PRE>
<P><P CLASS="Body"><A NAME="pgfId=182241"></A>Be careful not to confuse
the <CODE>'?'</CODE> in a UDP table (shorthand for <CODE>'0'</CODE> , <CODE>'1'</CODE>
, or <CODE>'x'</CODE> ) with the <CODE>'?'</CODE> in a constant that represents
an extension to <CODE>'z'</CODE> (Section 11.2.4) or the <CODE>'?'</CODE>
in a <CODE>case</CODE> statement that represents don't care values (<A HREF="CH11.08.htm#pgfId=1117">Section 11.8.1</A>).</P>
<P><P CLASS="Body"><A NAME="pgfId=8862"></A>For sequential UDP models that
need to detect edge transitions on inputs, there is another special truth-table
notation <CODE>(ab)</CODE> that represents a change in logic value from
<CODE>a</CODE> to <CODE>b</CODE> . For example, <CODE>(01)</CODE> represents
a rising edge. There are also shorthand notations for various edges:</P>
<UL>
<LI><A NAME="pgfId=6305"></A><CODE>* </CODE>is<CODE> (??)</CODE>
<LI><A NAME="pgfId=6306"></A><CODE>r </CODE>is<CODE> (01)</CODE>
<LI><A NAME="pgfId=6307"></A><CODE>f </CODE>is<CODE> (10)</CODE>
<LI><A NAME="pgfId=6308"></A><CODE>p </CODE>is<CODE> (01), (0x), </CODE>or<CODE>
(x1)</CODE>
<LI><A NAME="pgfId=6309"></A><CODE>n </CODE>is<CODE> (10), (1x), </CODE>or<CODE>
(x0)</CODE>
</UL>
<PRE>
<B>primitive</B> DFlipFlop(Q, Clock, Data);
<B>output</B> Q; <B>reg</B> Q; <B>input</B> Clock, Data;
<B>table </B>
//inputs : present state : output (next state)
r 0 : ? : 0 ; // rising edge, next state = output = 0
r 1 : ? : 1 ; // rising edge, next state = output = 1
(0x) 0 : 0 : 0 ; // rising edge, next state = output = 0
(0x) 1 : 1 : 1 ; // rising edge, next state = output = 1
(?0) ? : ? : - ; // falling edge, no change in output
? (??) : ? : - ; // no clock edge, no change in output
<B>endtable</B>
<B>endprimitive</B></PRE>
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