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<TITLE> 11.1 A Counter</TITLE>
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<H1>11.1 A Counter</H1>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=105914"></A>The following Verilog
code models a "black box" that contains a 50 MHz clock (period
20 ns), counts from 0 to 7, resets, and then begins counting at 0 again:</P>
<PRE><A HREF="../../Code/cd11b.htm#anchor26528003"><IMG SRC="../../Images/HDL.gif" WIDTH="32" HEIGHT="32" ALIGN="BOTTOM" NATURALSIZEFLAG="3"></A>
`timescale 1ns/1ns // Set the units of time to be nanoseconds.
<B>module </B>counter;
<B>reg</B> clock; // Declare a reg data type for the clock.
<B>integer</B> count; // Declare an integer data type for the count.
<B>initial</B> // Initialize things; this executes once at t=0.
begin
clock = 0; count = 0; // Initialize signals.
#340 $finish; // Finish after 340 time ticks.
<B> end</B>
/* An always statement to generate the clock; only one statement follows the always so we don't need a begin and an end. */
<B>always</B> #10 clock = ~ clock; // Delay (10ns) is set to half the clock cycle.
/* An always statement to do the counting; this executes at the same time (concurrently) as the preceding always statement. */
<B>always </B> <B>begin</B> // Wait here until the clock goes from 1 to 0.
@ (<B>negedge</B> clock);
// Now handle the counting.
<B>if</B> (count == 7)
count = 0;
<B>else</B> count = count + 1;
$display("time = ",$time," count = ", count);
<B>end</B>
<B>endmodule</B></PRE>
<P><P CLASS="Body"><A NAME="pgfId=60732"></A>Verilog <B>keywords</B> (reserved
words that are part of the Verilog language) are shown in bold type in the
code listings (but not in the text). References in this chapter such as
[<A HREF="../../Verilog/LRM/HTML/01/ch01.1.htm">Verilog LRM 1.1</A>] refer you
to the IEEE Verilog LRM.</P>
<P><P CLASS="Body"><A NAME="pgfId=46642"></A>The following output is from
the Cadence Verilog-XL simulator. This example includes the system input
so you can see how the tool is run and when it is finished. Some of the
banner information is omitted in the listing that follows to save space
(we can use "quiet" mode using a <CODE>'-q'</CODE> flag, but then
the version and other useful information is also suppressed):</P>
<PRE>
> verilog counter.v
VERILOG-XL 2.2.1 Apr 17, 1996 11:48:18
... Banner information omitted here...
Compiling source file "counter.v"
Highest level modules:
counter
time = 20 count = 1
time = 40 count = 2
(... 12 lines omitted...)
time = 300 count = 7
time = 320 count = 0
L10 "counter.v": $finish at simulation time 340
223 simulation events
CPU time: 0.6 secs to compile + 0.2 secs to link + 0.0 secs in simulation
End of VERILOG-XL 2.2.1 Apr 17, 1996 11:48:20
></PRE>
<P><P CLASS="Body"><A NAME="pgfId=46798"></A>Here is the output of the VeriWell
simulator from the console window (future examples do not show all of the
compiler output-- just the model output):</P>
<PRE>
Veriwell -k VeriWell.key -l VeriWell.log -s :counter.v
... banner information omitted ....
Memory Available: 0
Entering Phase I...
Compiling source file : :counter.v
The size of this model is [1%, 1%] of the capacity of the free version
Entering Phase II...
Entering Phase III...
No errors in compilation
Top-level modules:
counter
C1> .
time = 20 count = 1
time = 40 count = 2
(... 12 lines omitted...)
time = 300 count = 7
time = 320 count = 0
Exiting VeriWell for Macintosh at time 340
0 Errors, 0 Warnings, Memory Used: 29468
Compile time = 0.6, Load time = 0.7, Simulation time = 4.7
Normal exit
Thank you for using VeriWell for Macintosh</PRE>
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