ch11.04.htm
来自「介绍asci设计的一本书」· HTM 代码 · 共 121 行
HTM
121 行
<HTML>
<HEAD>
<META NAME="GENERATOR" CONTENT="Adobe PageMill 2.0 Mac">
<TITLE> 11.4 Hierarchy</TITLE>
</HEAD><!--#include file="top.html"--><!--#include file="header.html"--><br><!--#include file="AmazonAsic.html"-->
<P><A NAME="pgfId=71115"></A><HR ALIGN="LEFT"></P>
<P><A HREF="CH11.htm">Chapter start</A></P>
<P><A HREF="CH11.03.htm">Previous page</A></P>
<P><A HREF="CH11.05.htm">Next page</A></P>
<H1>11.4 Hierarchy</H1>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=71117"></A>The <B>module</B>
is the basic unit of code in the Verilog language [Verilog LRM 12.1],</P>
<PRE>
<B>module</B> holiday_1(sat, sun, weekend);
<B>input</B> sat, sun; <B>output</B> weekend;
<B>assign</B> weekend = sat | sun;
<B>endmodule</B></PRE>
<P><P CLASS="Body"><A NAME="pgfId=7107"></A>We do not have to explicitly
declare the scalar wires: <CODE>saturday</CODE> , <CODE>sunday</CODE> ,<CODE>
weekend</CODE> because, since these wires appear in the module interface,
they must be declared in an <CODE>input</CODE> , <CODE>output</CODE> , or
<CODE>inout</CODE> statement and are thus implicitly declared. The <B>module
interface</B> provides the means to interconnect two Verilog modules using
<B>ports</B> [Verilog LRM 12.3]. Each port must be explicitly declared
as one of <B>input</B>, <B>output</B>, or <B>inout</B>. <A HREF="#pgfId=85448">Table 11.3
</A>shows the characteristics of ports. Notice that a<CODE> reg</CODE> cannot
be an <CODE>input</CODE> port or an <CODE>inout</CODE> port. This is to
stop us trying to connect a<CODE> reg</CODE> to another <CODE>reg</CODE>
that may hold a different value.</P>
<P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
<TR>
<TD COLSPAN="4"><P CLASS="TableTitle"><A NAME="pgfId=85448"></A>TABLE 11.3 Verilog
ports.</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=85456"></A><B>Verilog port</B></TD>
<TD><P CLASS="Table"><A NAME="pgfId=85458"></A><B>input</B></TD>
<TD><P CLASS="Table"><A NAME="pgfId=85460"></A><B>output</B></TD>
<TD><P CLASS="Table"><A NAME="pgfId=85462"></A><B>inout</B></TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=85464"></A><B>Characteristics</B></TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=85500"></A><B>wire</B> (or other
net)</TD>
<TD><P><P CLASS="TableLeft"><A NAME="pgfId=85468"></A>reg or wire (or
other net)</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=85470"></A>We can read an output
port inside a module</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=85472"></A>wire (or other net)</TD></TR>
</TABLE>
<P CLASS="Body"><A NAME="pgfId=9727"></A>Within a module we may <B>instantiate</B>
other modules, but we cannot declare other modules. Ports are linked using
<B>named association</B> or <B>positional association</B>,</P>
<PRE>
`timescale 100s/1s // Units are 100 seconds with precision of 1s.
<B>module</B> life; <B>wire</B> [3:0] n; <B>integer</B> days;
<B>wire</B> wake_7am, wake_8am; // Wake at 7 on weekdays else at 8.
<B>assign</B> n = 1 + (days % 7); // n is day of the week (1-7)
<B>always</B>@(wake_8am or wake_7am)
$display("Day=",n," hours=%0d ",($time/36)%24," 8am = ",
wake_8am," 7am = ",wake_7am," m2.weekday = ", m2.weekday);
<B>initial</B> days = 0;
<B>initial</B> <B>begin</B> #(24*36*10);$finish; <B>end</B> // Run for 10 days.
<B>always</B> #(24*36) days = days + 1; // Bump day every 24hrs.
rest m1(n, wake_8am); // Module instantiation.
// Creates a copy of module rest with instance name m1,
// ports are linked using positional notation.
work m2(.weekday(wake_7am), .day(n));
// Creates a copy of module work with instance name m2,
// Ports are linked using named association.
<B>endmodule</B>
<B>module</B> rest(day, weekend); // Module definition.
// Notice the port names are different from the parent.
<B>input</B> [3:0] day; <B>output</B> weekend; <B>reg</B> weekend;
<B>always begin</B> #36 weekend = day > 5; <B>end</B> // Need a delay here.
<B>endmodule</B>
<B>module</B> work(day, weekday);
<B>input</B> [3:0] day; <B>output</B> weekday; <B>reg</B> weekday;
<B>always</B> <B>begin</B> #36 weekday = day < 6; <B>end</B> // Need a delay here.
<B>endmodule</B>
Day= 1 hours=0 8am = 0 7am = 0 m2.weekday = 0
Day= 1 hours=1 8am = 0 7am = 1 m2.weekday = 1
Day= 6 hours=1 8am = 1 7am = 0 m2.weekday = 0
Day= 1 hours=1 8am = 0 7am = 1 m2.weekday = 1</PRE>
<P><P CLASS="Body"><A NAME="pgfId=9825"></A>The port names in a module definition
and the port names in the parent module may be different. We can <B>associate</B>
(link or map) ports using the same order in the instantiating statement
as we use in the module definition--such as instance <CODE>m1 </CODE>in
module <CODE>life</CODE> . Alternatively we can associate the ports by naming
them--such as instance <CODE>m2</CODE> in module <CODE>life</CODE> (using
a period <CODE>'.'</CODE> before the port name that we declared in the module
definition). Identifiers in a module have local scope. If we want to refer
to an identifier outside a module, we use a <B>hierarchical name</B> [Verilog
LRM12.4] such as <CODE>m1.weekend</CODE> or <CODE>m2.weekday</CODE> (as
in module <CODE>life</CODE> ), for example. The compiler will first search
downward (or inward) then upward (outward) to resolve a hierarchical name
[Verilog LRM 12.4-12.5].</P>
<P><HR ALIGN="LEFT"></P>
<P><A HREF="CH11.htm">Chapter start</A></P>
<P><A HREF="CH11.03.htm">Previous page</A></P>
<P><A HREF="CH11.05.htm">Next page</A>
</BODY>
<!--#include file="Copyright.html"--><!--#include file="footer.html"-->
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?