ch11.14.htm
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<H1>11.14 Summary</H1>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=1291"></A>Table 11.13 lists
the key features of Verilog HDL. The most important concepts covered in
this chapter are:</P>
<P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
<TR>
<TD COLSPAN="2"><P CLASS="TableTitle"><A NAME="pgfId=7271"></A>TABLE 11.13 Verilog
on one page.</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=7275"></A><B> Verilog feature</B></TD>
<TD><P CLASS="Table"><A NAME="pgfId=7277"></A><B>Example</B></TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=7279"></A>Comments</TD>
<TD><PRE>
a = 0; // comment ends with newline
/* This is a multiline or block
comment */</PRE>
</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=7285"></A>Constants: string and numeric</TD>
<TD><PRE>
<B>parameter</B> BW = 32 // local, use BW
`define G_BUS 32 // global, use `G_BUS
4'b2 1'bx</PRE>
</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=7289"></A>Names (case-sensitive, start
with letter or '_')</TD>
<TD><PRE>
_12name A_name $BAD NotSame notsame </PRE>
</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=7293"></A>Two basic types of logic signals:
wire and reg</TD>
<TD><PRE>
<B>wire</B> myWire; <B>reg</B> myReg;</PRE>
</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=7299"></A>Use a continuous assignment
statement with wire</TD>
<TD><PRE>
<B>assign</B> myWire = 1;</PRE>
</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=7303"></A>Use a procedural assignment
statement with reg</TD>
<TD><PRE>
<B>always</B> myReg = myWire;</PRE>
</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=7307"></A>Buses and vectors use square
brackets</TD>
<TD><PRE>
<B>reg</B> [31:0] DBus; DBus[12] = 1'bx;</PRE>
</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=7312"></A>We can perform arithmetic
on bit vectors</TD>
<TD><PRE>
<B>reg</B> [31:0] DBus; DBus = DBus + 2;</PRE>
</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=7442"></A>Arithmetic is performed modulo
2<SUP CLASS="Superscript"> n</SUP></TD>
<TD><PRE>
<B>reg</B> [2:0] R; R = 7 + 1; // now R = 0</PRE>
</TD></TR>
<TR>
<TD><P CLASS="TableLeftEnd"><A NAME="pgfId=67530"></A>Operators: as in C (but
not <B>++</B> or <B>- -</B>)</TD>
<TD><PRE></PRE>
</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=7317"></A>Fixed logic-value system</TD>
<TD><PRE>
1, 0, x (unknown), z (high-impedance)</PRE>
</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=7321"></A>Basic unit of code is the
module</TD>
<TD><PRE>
<B>module</B> bake (chips, dough, cookies);
<B>input</B> chips, dough; <B>output</B> cookies;
assign cookies = chips & dough;
<B>endmodule</B></PRE>
</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=7328"></A>Ports</TD>
<TD><P><P CLASS="TableLeft"><A NAME="pgfId=7330"></A>input or input/output ports
are wire</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=7331"></A>output ports are wire or
reg</TD></TR>
<TR>
<TD><P><P CLASS="TableLeft"><A NAME="pgfId=7333"></A>Procedures model things
that happen at the same time</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=105628"></A>and may be sensitive
to an edge, <B>posedge</B>, <B>negedge</B>,</P>
<P><P CLASS="TableLeft"><A NAME="pgfId=105629"></A>or to a level.</TD>
<TD><PRE>
<B>always</B> @rain sing; <B>always </B>@rain dance;
<B>always</B> @(<B>posedge</B> clock) D = Q; // flop
<B>always</B> @(a <B>or</B> b) c = a & b; // and gate</PRE>
</TD></TR>
<TR>
<TD><P><P CLASS="TableLeftEnd"><A NAME="pgfId=7338"></A>Sequential blocks model
repeating things:</P>
<P><P CLASS="TableLeftEnd"><A NAME="pgfId=59050"></A><B>always</B>: executes
forever</P>
<P><P CLASS="TableLeftEnd"><A NAME="pgfId=59051"></A><B>initial</B>: executes
once only at start of simulation</TD>
<TD><PRE>
<B>initial</B> born;
<B>always</B> @alarm_clock <B>begin</B> : a_day
metro=commute; bulot=work; dodo=sleep;
<B>end</B></PRE>
</TD></TR>
<TR>
<TD><P CLASS="TableLeftEnd"><A NAME="pgfId=59021"></A>Functions and tasks</TD>
<TD><PRE>
<B>function</B> ... <B>endfunction</B>
<B>task</B> ... <B>endtask</B></PRE>
</TD></TR>
<TR>
<TD><P CLASS="TableLeftEnd"><A NAME="pgfId=59025"></A>Output</TD>
<TD><PRE>
$display("a=%f",a);$dumpvars;$monitor(a)</PRE>
</TD></TR>
<TR>
<TD><P CLASS="TableLeftEnd"><A NAME="pgfId=59029"></A>Control simulation</TD>
<TD><PRE>
$stop; $finish // sudden or gentle halt</PRE>
</TD></TR>
<TR>
<TD><P CLASS="TableLeftEnd"><A NAME="pgfId=59066"></A>Compiler directives</TD>
<TD><P CLASS="TableLeftEnd"><A NAME="pgfId=59068"></A>`timescale 1ns/1ps //
units/resolution</TD></TR>
<TR>
<TD><P CLASS="TableLeftEnd"><A NAME="pgfId=59070"></A>Delay</TD>
<TD><P><P CLASS="TableLeftEnd"><A NAME="pgfId=59072"></A>#1 a = b; //
delay then sample b</P>
<P><P CLASS="TableLeftEnd"><A NAME="pgfId=67515"></A>a = #1 b; //
sample b then delay</TD></TR>
</TABLE>
</P>
<UL>
<LI><A NAME="pgfId=59714"></A>Concurrent processes and sequential execution
<LI><A NAME="pgfId=59719"></A>Difference between a <CODE>reg</CODE> and
a <CODE>wire</CODE> , and between a scalar and a vector
<LI><A NAME="pgfId=66178"></A>Arithmetic operations on <CODE>reg</CODE>
and <CODE>wire</CODE>
<LI><A NAME="pgfId=67503"></A>Data slip
<LI><A NAME="pgfId=67504"></A>Delays and events
</UL>
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