ch11.15.htm
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in the timing check condition may be <B>deterministic</B> (using <CODE>===</CODE>
, <CODE>!==</CODE> , <CODE>~</CODE> , or no operator) or <B>nondeterministic</B>
(using <CODE>==</CODE> or <CODE>!=</CODE> ). For deterministic comparisons,
an <CODE>'x'</CODE> result disables the timing check. For nondeterministic
comparisons, an <CODE>'x'</CODE> result enables the timing check.</P>
<P><P CLASS="Body"><A NAME="pgfId=122587"></A>As an example the following
<B>unconditioned timing check</B>,</P>
<PRE>
$setup(data, <B>posedge</B> clock, 10);</PRE>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=122589"></A>performs a setup
timing check on every positive edge of <CODE>clock</CODE> , as was explained
in Section 11.13.3. The following controlled timing check is enabled
only when <CODE>clear</CODE> is high, which is what is required in a flip-flop
model, for example.</P>
<PRE>
$setup(data, <B>posedge</B> clock &&& clear, 10);</PRE>
<P><P CLASS="Body"><A NAME="pgfId=122592"></A>The next example shows two
alternative ways to enable a timing check only when <CODE>clear</CODE> is
low. The second method uses a nondeterministic operator.</P>
<PRE>
$setup(data,<B>posedge</B> clock &&&(~clear),10); // clear=x disables check
$setup(data,<B>posedge</B> clock &&&(clear==0),10); // clear=x enables check</PRE>
<P><P CLASS="Body"><A NAME="pgfId=122595"></A>To perform the setup check
only when <CODE>clear</CODE> and <CODE>preset</CODE> signals are high, you
can add a gate outside the specify block, as follows:</P>
<PRE>
and g1(clear_and_preset, clear, set);</PRE>
<P><P CLASS="Exercise"><A NAME="pgfId=122597"></A>A controlled timing check
event can then use this <CODE>clear_and_preset</CODE> signal:</P>
<PRE>
$setup(data, <B>posedge</B> clock &&& clear_and_preset, 10);</PRE>
<P><P CLASS="Body"><A NAME="pgfId=122863"></A>Use the preceding techniques
to expand the D flip-flop model, dff_udp, from Section 11.13.3 to include
asynchronous active-low preset and clear signals as well as an output, <CODE>qbar</CODE>
. Use the following module interface:</P>
<PRE>
module dff(q, qbar, clock, data, preset, clear);</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=137532"></A>11.48 (Verilog
BNF, 30 min.) Here is the "old" BNF definition of a sequential
block (used in the Verilog reference manuals and the OVI LRM). Are there
any differences from the "new" version?</P>
<PRE>
<sequential_block> ::=
<B>begin</B> <statement>* <B>end</B>
or
<B>begin</B>: <block_IDENTIFIER> <block_declaration>*
<statement>*
<B>end</B>
<block_declaration> ::= <B>parameter</B> <list_of_param_assignment>;
or <B>reg</B> <range>? <attribute_decl>*
<list_of_register_variable>;
or <B>integer</B> <attribute_decl>* <list_of_register_variable>;
or <B>real</B> <attribute_decl>* <list_of_variable_IDENTIFIER>;
or <B>time</B> <attribute_decl>* <list_of_register_variable>;
or <B>event</B> <attribute_decl>* <list_of_event_IDENTIFIER>;
<statement> ::=
<blocking_assignment>;
or <non-blocking_assignment>;
or <B>if</B>(<expression>) <statement_or_null>
<<B>else</B> <statement_or_null> >?
or <<B>case</B> or <B>casez</B> or <B>casex</B>>
(<expression>) <case item>+ <B>endcase</B>
or <B>forever</B> <statement>
or <B>repeat</B>(<expression>) <statement>
or <B>while</B>(<expression>) <statement>
or <B>for</B>(<assignment>;
<expression>; <assignment>) <statement>
or <B>wait</B>(<expression>) <statement_or_null>
or <B>disable</B> <task_IDENTIFIER>;
or <B>disable</B> <block_IDENTIFIER>;
or <B>force</B> <assignment>; or <B>release</B> <value>;
or <timing_control> <statement_or_null>
or -> <event_IDENTIFIER>;
or <sequential_block> or <parallel_block>
or <task_enable> or <system_task_enable></PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=163540"></A>11.49 (Conditional
compiler directives, 30 min.) The conditional compiler directives: <CODE>`define</CODE>
, <CODE>`ifdef</CODE> , <CODE>`else</CODE> , <CODE>`endif</CODE> , and <CODE>`undef</CODE>
; work much as in C. Write and compile a module that models an AND gate
as 'z = a&b' if the variable behavioral is defined. If behavioral is
not defined, then model the AND gate as 'and a1 (z, a, b)'.</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=163546"></A>11.50 (*Macros,
30 min.) According to the IEEE Verilog LRM [16.3.1] you can create a <B>macro</B>
with parameters using<CODE> `define</CODE> , as the following example illustrates.
This is a particularly difficult area of compliance. Does your software
allow the following? You may have to experiment considerably to get this
to work. Hint: Check to see if your software is substituting for the macro
text literally or if it does in fact substitute for parameters.</P>
<PRE>
`define M_MAX(a, b)((a) > (b) ? (a) : (b))
`define M_ADD(a,b) (a+b)
<B>module</B> macro;
<B>reg</B> m1, m2, m3, s0, s1;
`define var_nand(delay) nand #delay
`var_nand (2) g121 (q21, n10, n11);
`var_nand (3) g122 (q22, n10, n11);
<B>initial</B> <B>begin </B>s0=0; s1=1;
m1 = `M_MAX (s0, s1); m2 = `M_ADD (s0,s1); m3 = s0 > s1 ? s0 : s1;
<B>end</B>
<B>initial</B> #1 $display(" m1=",m1," m2=",m2," m3=",m3);
<B>endmodule</B></PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=139515"></A>11.51 (**Verilog
hazards, 30 min.) The MTI simulator, VSIM, is capable of detecting the following
kinds of Verilog hazards:</P>
<OL>
<LI><A NAME="pgfId=139517"></A>WRITE/WRITE: Two processes writing to the
same variable at the same time.
<LI><A NAME="pgfId=139519"></A>READ/WRITE: One process reading a variable
at the same time it is being written to by another process. VSIM calls
this a READ/WRITE hazard if it executed the read first.
<LI><A NAME="pgfId=139523"></A>WRITE/READ: Same as a READ/WRITE hazard
except that VSIM executed the write first.
</OL>
<P><P CLASS="Exercise"><A NAME="pgfId=139346"></A>For example, the following
log shows how to simulate Verilog code in hazard mode for the example in
Section 11.6.2:</P>
<PRE>
> vlib work
> vlog -hazards data_slip_1.v
> vsim -c -hazards data_slip_1
...(lines omitted)...
# 100 0 1 1 x
# ** Error: Write/Read hazard detected on Q1 (ALWAYS 3 followed by ALWAYS 4)
# Time: 150 ns Iteration: 1 Instance:/
# 150 1 1 1 1
...(lines omitted)...</PRE>
<P><P CLASS="Exercise"><A NAME="pgfId=161472"></A>There are a total of five
hazards in the module data_slip_1, four are on Q1, but there is another.
If you correct the code as suggested in Section 11.6.2 and run VSIM,
you will find this fifth hazard. If you do not have access to MTI's simulator,
can you spot this additional read/write hazard? Hint: It occurs at time
zero on Clk. Explain.</P>
<H2><A NAME="pgfId=161480"></A>11.15.1 The Viterbi Decoder</H2>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=161485"></A>11.52 (Understanding,
20 min.) Calculate the values shown in Table 11.8 if we use 4
bits for the distance measures instead of 3.</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=149711"></A>11.53 (Testbenches)</P>
<P><P CLASS="ExercisePartFirst"><A NAME="pgfId=184147"></A>a. (30 min.) Write
a testbench for the encoder, viterbi_encode, in Section 11.12 and reproduce
the results of Table 11.7.</P>
<P><P CLASS="ExercisePart"><A NAME="pgfId=184148"></A>b. (30 min.)
Write a testbench for the receiver front-end viterbi_distances and reproduce
the results of Table 11.9 (you can write this stand-alone or use the
answer to part a to generate the input). Hint: You will need a model for
a D flip-flop. The sequence of results is more important than the exact
timing. If you do have timing differences, explain them carefully.</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=149923"></A>11.54 (Things
go wrong, 60 min.) Things do not always go as smoothly as the examples in
this book might indicate. Suppose you accidentally invert the sense of the
reset for the D flip-flops in the encoder. Simulate the output of the faulty
encoder with an input sequence X<SUB CLASS="Subscript"> n</SUB> = 0, 1, 2, 3,
... (in other words run the encoder with the flip-flops being reset continually).
The output sequence looks reasonable (you should find that it is Y<SUB CLASS="Subscript">
n</SUB> = 0, 2, 4, 6, ...). Explain this result using the
state diagram of Figure 11.3. If you had constructed a testbench for
the entire decoder and did not check the intermediate signals against expected
values you would probably never find this error.</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=161074"></A>11.55 (Subset
decoder) Table 11.21 shows the inputs and outputs from the first-stage
of the Viterbi decoder, the subset decoder. Calculate the expected output
and then confirm your predictions using simulation.</P>
<P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
<TR>
<TD COLSPAN="17"><P CLASS="TableTitle"><A NAME="pgfId=161082"></A>TABLE 11.21 Subset
decoder (Problem 11.55).</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=161116"></A>input</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161118"></A>in0</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161120"></A>in1</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161122"></A>in2</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161124"></A>in3</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161126"></A>in4</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161128"></A>in5</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161130"></A>in6</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161132"></A>in7</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161134"></A>s0</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161136"></A>s1</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161138"></A>s2</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161140"></A>s3</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161142"></A>sout0</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161144"></A>sout1</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161146"></A>sout2</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161148"></A>sout3</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=161150"></A>5</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161152"></A>6</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161154"></A>7</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161156"></A>6</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161158"></A>4</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161160"></A>1</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161162"></A>0</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161164"></A>1</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161166"></A>4</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161168"></A>1</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161170"></A>0</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161172"></A>1</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161174"></A>4</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161176"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=161178"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=161180"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=161182"></A> </TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=161184"></A>4</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161186"></A>7</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161188"></A>6</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161190"></A>4</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161192"></A>1</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161194"></A>0</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161196"></A>1</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161198"></A>4</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161200"></A>6</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161202"></A>0</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161204"></A>1</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161206"></A>4</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161208"></A>1</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161210"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=161212"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=161214"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=161216"></A> </TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=161218"></A>1</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161220"></A>1</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161222"></A>0</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161224"></A>1</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161226"></A>4</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161228"></A>6</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161230"></A>7</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161232"></A>6</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161234"></A>4</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161236"></A>1</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161238"></A>0</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161240"></A>1</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161242"></A>4</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161244"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=161246"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=161248"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=161250"></A> </TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=161252"></A>0</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161254"></A>0</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161256"></A>1</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161258"></A>4</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161260"></A>6</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161262"></A>7</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161264"></A>6</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161266"></A>4</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161268"></A>1</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161270"></A>0</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161272"></A>1</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161274"></A>4</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161276"></A>1</TD>
<TD><P CLASS="Table"><A NAME="pgfId=161278"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=161280"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=161282"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=161284"></A> </TD></TR>
</TABLE>
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