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<B>end</B>
<B>assign</B> ScOut=Q[width-1];
<B>endmodule</B></PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=161636"></A>11.30 (Pads,
30 min.) Test the following model for a bidirectional I/O pad:</P>
<PRE>
<B>module</B> PadBidir (C, Pad, I, Oen); // active low enable
<B>parameter</B> width=1, pinNumbers="", \strength =1, level="CMOS",
pull="none", externalVdd=5;
<B>output</B> [width-1:0] C; <B>inout</B> [width-1:0] Pad; <B>input</B> [width-1:0] I;
<B>input</B> Oen;
<B>assign</B> #1 Pad = Oen ? {width{1'bz}} : I;
<B>assign</B> #1 C = Pad;
<B>endmodule</B></PRE>
<P><P CLASS="Exercise"><A NAME="pgfId=162002"></A>Construct and test a model
for a three-state pad from the above.</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=161582"></A>11.31 (Loops,
15 min.) Explain and correct the problem in the following code:</P>
<PRE>
<B>module</B> Loop_Bad; <B>reg</B> [3:0] i; <B>reg</B> [31:0] DBus;
<B>initial</B> DBus = 0;
<B>initial</B> <B>begin</B> #1; <B>for</B> (i=0; i<=15; i=i+1) DBus[i]=1; <B>end</B>
<B>initial</B> <B>begin</B>
$display("DBus = %b",DBus); #2; $display("DBus = %b",DBus); $stop;
<B>end endmodule</B></PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=173918"></A>11.32 (Arithmetic,
10 min.) Explain the following:</P>
<PRE>
<B>integer</B> IntA;
IntA = -12 / 3; // result is -4
IntA = -'d 12 / 3; // result is 1431655761</PRE>
<P><P CLASS="Exercise"><A NAME="pgfId=173928"></A>Determine and explain
the values of <CODE>intA</CODE> and <CODE>regA</CODE> after each assignment
statement in the following code:</P>
<PRE>
<B>integer</B> intA; <B>reg</B> [15:0] regA;
intA = -4'd12; regA = intA/3; regA = -4'd12;
intA = regA/3; intA = -4'd12/3; regA = -12/3;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=70060"></A>11.33 (Arithmetic
overflow, 30 min.) Consider the following:</P>
<PRE>
<B>reg</B> [7:0] a, b, sum; sum = (a + b) >> 1;</PRE>
<P><P CLASS="Exercise"><A NAME="pgfId=70067"></A>The intent is to add <CODE>a</CODE>
and <CODE>b</CODE> , which may cause an overflow, and then shift <CODE>sum</CODE>
to keep the carry bit. However, because all operands in the expression are
of an 8-bit width, the expression<CODE> (a + b) </CODE>is only 8 bits wide,
and we lose the carry bit before the shift. One solution forces the expression
<CODE>(a + b)</CODE> to use at least 9 bits. For example, adding an integer
value of 0 to the expression will cause the evaluation to be performed using
the bit size of integers [LRM 4.4.2]. Check to see if the following alternatives
produce the intended result:</P>
<PRE>
sum = (a + b + 0) >> 1;
sum = {0,a} + {0,b} >> 1;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=70081"></A>11.34 (*Data slip,
60 min.) Table 11.20 shows several different ways to model the connection
of a 2-bit shift register. Determine which of these models suffer from data
slip. In each case show your simulation results.</P>
<P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
<TR>
<TH COLSPAN="3"><P CLASS="TableTitle"><A NAME="pgfId=200600"></A>TABLE 11.20 Data
slip (Problem 11.34).</TH></TR>
<TR>
<TH><P CLASS="TableLeft"><A NAME="pgfId=200606"></A> </TH>
<TH><P CLASS="TableLeft"><A NAME="pgfId=200608"></A>Alternative</TH>
<TH><P CLASS="Table"><A NAME="pgfId=200610"></A>Data slip?</TH></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=200612"></A>1</TD>
<TD><PRE>
<B>always</B> @(<B>posedge</B> Clk) <B>begin</B> Q2 = Q1; Q1 = D1; <B>end</B></PRE>
</TD>
<TD><P CLASS="Table"><A NAME="pgfId=200616"></A> </TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=200618"></A>2</TD>
<TD><PRE>
<B>always</B> @(<B>posedge</B> Clk) <B>begin</B> Q1 = D1; Q2 = Q1; <B>end</B></PRE>
</TD>
<TD><P CLASS="Table"><A NAME="pgfId=200622"></A> </TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=200624"></A>3</TD>
<TD><PRE>
<B>always</B> @(<B>posedge</B> Clk) <B>begin</B> Q1 <= #1 D1; Q2 <= #1 Q1; <B>end</B></PRE>
</TD>
<TD><P CLASS="Table"><A NAME="pgfId=200628"></A> </TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=200630"></A>4</TD>
<TD><PRE>
<B>always</B> @(<B>posedge</B> Clk) Q1 = D1; <B>always</B> @(<B>posedge</B> Clk) Q2 = Q1;</PRE>
</TD>
<TD><P CLASS="Table"><A NAME="pgfId=200634"></A>Y</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=200636"></A>5</TD>
<TD><PRE>
<B>always</B> @(<B>posedge</B> Clk) Q1 = #1 D1; <B>always</B> @(<B>posedge</B> Clk) Q2 = #1 Q1;</PRE>
</TD>
<TD><P CLASS="Table"><A NAME="pgfId=200640"></A>N</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=200642"></A>6</TD>
<TD><PRE>
<B>always</B> @(<B>posedge</B> Clk) #1 Q1 = D1; <B>always</B> @(<B>posedge</B> Clk) #1 Q2 = Q1;</PRE>
</TD>
<TD><P CLASS="Table"><A NAME="pgfId=200646"></A> </TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=200648"></A>7</TD>
<TD><PRE>
<B>always</B> @(<B>posedge</B> Clk) Q1 <= D1; <B>always</B> @(<B>posedge</B> Clk) Q2 <= Q1;</PRE>
</TD>
<TD><P CLASS="Table"><A NAME="pgfId=200652"></A> </TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=200654"></A>8</TD>
<TD><PRE>
<B>module</B> FF_1 (Clk, D1, Q1); <B>always</B> @(<B>posedge</B> Clk) Q1 = D1; <B>endmodule</B>
<B>module</B> FF_2 (Clk, Q1, Q2); <B>always</B> @(<B>posedge</B> Clk) Q2 = Q1; <B>endmodule</B></PRE>
</TD>
<TD><P CLASS="Table"><A NAME="pgfId=200659"></A> </TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=200661"></A>9</TD>
<TD><PRE>
<B>module</B> FF_1 (Clk, D1, Q1); <B>always</B> @(<B>posedge</B> Clk) Q1 <= D1; <B>endmodule</B>
<B>module</B> FF_2 (Clk, Q1, Q2); <B>always</B> @(<B>posedge</B> Clk) Q2 <= Q1; <B>endmodule</B></PRE>
</TD>
<TD><P CLASS="Table"><A NAME="pgfId=200666"></A> </TD></TR>
</TABLE>
<P CLASS="ExerciseHead"><A NAME="pgfId=106756"></A>11.35 (**Timing,
30 min.) What does a simulator display for the following?</P>
<PRE>
<B>assign</B> p = q; <B>initial</B> <B>begin</B> q = 0; #1 q = 1; $display(p); <B>end</B></PRE>
<P><P CLASS="Exercise"><A NAME="pgfId=160557"></A>What is the problem here?
Conduct some experiments to illustrate your answer.</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=70097"></A>11.36 (Port connections,
10 min.) Explain the following declaration:</P>
<PRE>
<B>module</B> test (.a(c), .b(c));</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=70110"></A>11.37 (**Functions
and tasks, 30 min.) Experiment to determine whether invocation of a function
(or task) behaves as a blocking or nonblocking assignment.</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=70112"></A>11.38 (Nonblocking
assignments, 10 min.) Predict the output of the following model:</P>
<PRE>
<B>module</B> e1; <B>reg</B> a, b, c;
<B>initial</B> <B>begin </B>a = 0; b = 1; c = 0; <B>end </B>
<B>always </B>c = #5 ~c; <B>always</B> @(<B>posedge</B> c) <B>begin </B>a <= b; b <= a; <B>end</B>
<B>endmodule </B></PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=70106"></A>11.39 (Assignment
timing, 20 min.) Predict the output of the following module and explain
the timing of the assignments:</P>
<PRE>
<B>module</B> e2; <B>reg</B> a, b, c, d, e, f;
<B>initial</B> <B>begin </B>a = #10 1; b = #2 0; c = #4 1; <B>end </B>
<B>initial</B> <B>begin </B>d <= #10 1; e <= #2 0; f <= #4 1; <B>end </B>
<B>endmodule </B></PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=70093"></A>11.40 (Swap, 10
min.) Explain carefully what happens in the following code:</P>
<PRE>
<B>module</B> e3; <B>reg</B> a, b;
<B>initial</B> <B>begin </B>a = 0; b = 1; a <= b; b <= a; <B>end </B>
<B>endmodule</B></PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=70088"></A>11.41 (*Overwriting,
30 min.) Explain the problem in the following code, determine what happens,
and conduct some experiments to explore the problem further:</P>
<PRE>
<B>module</B> m1; <B>reg</B> a;
<B>initial</B> a = 1;
<B>initial begin </B>a <= #4 0; a <= #4 1; <B>end </B>
<B>endmodule</B></PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=70204"></A>11.42 (*Multiple
assignments, 30 min.) Explain what happens in the following:</P>
<PRE>
<B>module</B> m2; <B>reg</B> r1; <B>reg</B> [2:0] i;
<B>initial</B> <B>begin </B>
r1 = 0; <B>for</B> (i = 0; i <= 5; i = i+1) r1 <= # (i*10) i[0]; <B>end</B>
<B>endmodule</B></PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=70252"></A>11.43 (Timing,
30 min) Write a model to mimic the behavior of a traffic light signal. The
clock input is 1 MHz. You are to drive the lights as follows (times that
the lights are on are shown in parentheses): green (60 s), yellow (1 s),
red (60 s).</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=104850"></A>11.44 (Port declarations,
30 min.) The rules for port declarations are as follows: "The port
expression in the port definition can be one of the following:</P>
<UL>
<LI><A NAME="pgfId=104878"></A>a simple identifier
<LI><A NAME="pgfId=104879"></A>a bit-select of a vector declared within
the module
<LI><A NAME="pgfId=104880"></A>a part-select of a vector declared within
the module
<LI><A NAME="pgfId=104881"></A>a concatenation of any of the above
</UL>
<P><P CLASS="Exercise"><A NAME="pgfId=104851"></A>Each port listed in the
module definition's list of ports shall be declared in the body of the module
as an input, output, or inout (bidirectional). This is in addition to any
other declaration for a particular port--for example, a reg, or wire. A
port can be declared in both a port declaration and a net or register declaration.
If a port is declared as a vector, the range specification between the two
declarations of a port shall be identical" [Verilog LRM 12.3.2].</P>
<P><P CLASS="Exercise"><A NAME="pgfId=104887"></A>Compile the following
and comment (you may be surprised at the results):</P>
<PRE>
<B>module</B> stop (); <B>initial</B> #1 $finish; <B>endmodule</B>
<B>module</B> Outs_1 (a); <B>output</B> [3:0] a; <B>reg</B> [3:0] a;
<B>initial</B> a <= 4'b10xz; <B>endmodule</B>
<B>module</B> Outs_2 (a); <B>output</B> [2:0] a; <B>reg</B> [3:0] a;
<B>initial</B> a <= 4'b10xz; <B>endmodule</B>
<B>module</B> Outs_3 (a); <B>output</B> [3:0] a; <B>reg</B> [2:0] a;
<B>initial</B> a <= 4'b10xz; <B>endmodule</B>
<B>module</B> Outs_4 (a); <B>output</B> [2:0] a; <B>reg</B> [2:0] a;
<B>initial</B> a <= 4'b10xz; <B>endmodule</B>
<B>module</B> Outs_5 (a); <B>output</B> a; <B>reg</B> [3:0] a;
<B>initial</B> a <= 4'b10xz; <B>endmodule</B>
<B>module</B> Outs_6 (a[2:0]); <B>output</B> [3:0] a; <B>reg</B> [3:0] a;
<B>initial</B> a <= 4'b10xz; <B>endmodule</B>
<B>module</B> Outs_7 (a[1]); <B>output</B> [3:0] a; <B>reg</B> [3:0] a;
<B>initial</B> a <= 4'b10xz; <B>endmodule</B>
<B>module</B> Outs_8 (a[1]); <B>output</B> a; <B>reg</B> [3:0] a;
<B>always</B> a <= 4'b10xz; <B>endmodule</B></PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=136551"></A>11.45 (Specify
blocks, 30 min.)</P>
<P><P CLASS="ExercisePartFirst"><A NAME="pgfId=184130"></A>a. Describe
the pin-to-pin timing of the following module. Build a testbench to demonstrate
your explanation.</P>
<PRE>
<B>module</B> XOR_spec (a, b, z); <B>input</B> a, b: <B>output</B> z; <B>xor</B> x1 (z, a, b);
<B>specify</B>
<B>specparam</B> tnr = 1, tnf = 2 <B>specparam</B> tir = 3, tif = 4;
<B>if</B> ( a)(b<B> </B>=> z) = (tir, tif); <B>if</B> ( b)(a<B> </B>=> z) = (tir, tif);
<B>if</B> (~a)(b<B> </B>=> z) = (tnr, tnf); <B>if</B> (~b)(a<B> </B>=> z) = (tnr, tnf);
<B>endspecify</B>
<B>endmodule </B></PRE>
<P><P CLASS="ExercisePart"><A NAME="pgfId=136633"></A>b. Write and
test a module for a 2:1 MUX with inputs <CODE>A0</CODE> , <CODE>A1</CODE>
, and <CODE>sel</CODE> ; output <CODE>Z</CODE> ; and the following delays:
<CODE>A0</CODE> to <CODE>Z</CODE> : 0.3 ns (rise) and 0.4 ns (fall); <CODE>A1</CODE>
to <CODE>Z</CODE> : 0.2 ns (rise) and 0.3 ns (fall); <CODE>sel</CODE> to
<CODE>Z</CODE> = 0.5 ns.</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=113068"></A>11.46 (Design
contest, **60 min.) In 1995 John Cooley organized a contest between VHDL
and Verilog for ASIC designers. The goal was to design the fastest 9-bit
counter in under one hour using Synopsys synthesis tools and an LSI Logic
vendor technology library. The Verilog interface is as follows:</P>
<PRE>
<B>module</B> counter (data_in, up, down, clock,
count_out, carry_out, borrow_out, parity_out);
<B>output</B> [8:0] count_out;
<B>output</B> carry_out, borrow_out, parity_out;
<B>input</B> [8:0] data_in; input clock, up, down;
<B>reg</B> [8:0] count_out; reg carry_out, borrow_out, parity_out;
// Insert your design here.
<B>endmodule</B></PRE>
<P><P CLASS="Exercise"><A NAME="pgfId=160999"></A>The counter is positive-edge
triggered, counts up with <CODE>up='1'</CODE> and down with <CODE>down='1'</CODE>
. The contestants had the advantage of a predefined testbench with a set
of test vectors; you do not. Design a model for the counter and a testbench.</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=122575"></A>11.47 (Timing
checks, ***60 min.+) Flip-flops with preset and clear require more complex
timing-check constructs than those described in Section 11.13.3. The
following BNF defines a <B>controlled timing-check event</B>:</P>
<PRE>
controlled_timing_check_event ::= timing_check_event_control specify_terminal_descriptor [ &&& timing_check_condition ]
timing_check_condition ::=
scalar_expression | ~scalar_expression
| scalar_expression == scalar_constant
| scalar_expression === scalar_constant
| scalar_expression != scalar_constant
| scalar_expression !== scalar_constant</PRE>
<P><P CLASS="Body"><A NAME="pgfId=122582"></A>The scalar expression that
forms the conditioning signal must be a scalar net, or else the least significant
bit of a vector net or a multibit expression value is used. The comparisons
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