ch11.15.htm
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<P><P CLASS="Exercise"><A NAME="pgfId=5892"></A>These next two modules change
the parameter value by using a <CODE>defparam</CODE> statement, which overrides
the declared parameter value:</P>
<PRE>
<B>module</B> X_AND_Gates(OutBus, InBusA, InBusB);
<B>parameter</B> X = 2;<B>input</B> [X-1:0] InBusA, InBusB;<B>output</B> [X-1:0] OutBus;
Vector_AND #(X) My_AND(OutBus, InBusA, InBusB);
<B>endmodule</B>
<B>module</B> size; <B>defparam </B>X_AND_Gates.X = 4; <B>endmodule</B></PRE>
<P><P CLASS="ExercisePartFirst"><A NAME="pgfId=5878"></A>a. Check that
the two alternative methods of specifying parameters are equivalent by instantiating
the modules <CODE>Four_AND_Gates</CODE> and <CODE>X_AND_Gates</CODE> in
another module and simulating.</P>
<P><P CLASS="ExercisePart"><A NAME="pgfId=99588"></A>b. List and comment
on the advantages and disadvantages of both methods.</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=6190"></A>11.16 (Default
Verilog delays, 10 min.). Demonstrate, using simulation, that the following
NAND gates have the delays you expect:</P>
<PRE>
<B>nand</B> (strong0, strong1) #1
Nand_1(n001, n004, n005),
Nand_2(n003, n001, n005, n002);
<B>nand</B> (n006, n005, n002);</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=150103"></A>11.17 (Arrays
of modules, 30 min.) Newer versions of Verilog allow the instantiating of
<B>arrays of modules</B> (in this book we usually call this a vector since
we are only allowed one row). You specify the number in the array by using
a <B>range</B> after the instance name as follows:</P>
<PRE>
<B>nand</B> #2 nand_array[0:7](zn, a, b);</PRE>
<P><P CLASS="Exercise"><A NAME="pgfId=150104"></A>Create and test a model
for an 8-bit register using an array of flip-flops.</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=6191"></A>11.18 (Assigning
Verilog real to integer data types, 10 min.). What is the value of <CODE>ImInteger</CODE>
in the following code?</P>
<PRE>
<B>real</B> ImReal; <B>integer</B> ImInteger;
<B>initial</B> <B>begin </B>ImReal = -1.5; ImInteger = ImReal; <B>end</B></PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=61349"></A>11.19 (BNF syntax,
10 min.) Use the BNF syntax definitions in Appendix B to answer the
following questions. In each case explain how you arrive at the answer:</P>
<P><P CLASS="ExercisePartFirst"><A NAME="pgfId=106222"></A>a. What
is the highest-level construct?</P>
<P><P CLASS="ExercisePart"><A NAME="pgfId=160477"></A>b. What is the
lowest-level construct?</P>
<P><P CLASS="ExercisePart"><A NAME="pgfId=160470"></A>c. Can you nest
<CODE>begin</CODE> and <CODE>end</CODE> statements?</P>
<P><P CLASS="ExercisePart"><A NAME="pgfId=106223"></A>d. Where is a
legal place for a <CODE>case</CODE> statement?</P>
<P><P CLASS="ExercisePart"><A NAME="pgfId=160463"></A>e. Is the following
code legal: <B>reg</B><CODE> [31:0] rega, [32:1] regb;</CODE></P>
<P><P CLASS="ExercisePart"><A NAME="pgfId=160466"></A>f. Where is it
legal to include sequential statements?</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=10832"></A>11.20 (Old syntax
definitions, 10 min.) Prior to the IEEE LRM, Verilog BNF was expressed using
a different notation. For example, an event expression was defined as follows:</P>
<PRE>
<event_expression> ::= <expression>
or <<<B>posedge</B> or <B>negedge</B>> <SCALAR_EVENT_EXPRESSION>>
or <<event_expression> <B>or</B> <event_expression>></PRE>
<P><P CLASS="Exercise"><A NAME="pgfId=10916"></A>Notice that we are using
<CODE>'or'</CODE> as part of the BNF to mean "alternatively" and
also <CODE>'</CODE> <B>or</B><CODE> '</CODE> as a Verilog keyword. The keyword
<CODE>'</CODE> <B>or</B><CODE> '</CODE> is in bold--the difference is fairly
obvious. Here is an alternative definition for an event expression:</P>
<PRE>
<event_expression> ::= <expression>
||= <B>posedge</B> <SCALAR_EVENT_EXPRESSION>
||= <B>negedge</B> <SCALAR_EVENT_EXPRESSION>
||= <event_expression> <<B>or</B> <event_expression>>*</PRE>
<P><P CLASS="Exercise"><A NAME="pgfId=200725"></A>Are these definitions
equivalent (given, of course, that we replaced <CODE>||=</CODE> with <CODE>or</CODE>
in the simplified syntax)? Explain carefully how you would attempt to prove
that they are the same.</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=200786"></A>11.21 (Operators,
20 min.) Explain Table 11.17 (see next page).</P>
<P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
<TR>
<TD COLSPAN="5"><P CLASS="TableTitle"><A NAME="pgfId=200739"></A>TABLE 11.17 Unary
operators (Problem 11.21).</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=200749"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=200751"></A>(a)</TD>
<TD><P CLASS="Table"><A NAME="pgfId=200753"></A>(b)</TD>
<TD><P CLASS="Table"><A NAME="pgfId=200755"></A>(c)</TD>
<TD><P CLASS="Table"><A NAME="pgfId=200757"></A>(d)</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=200759"></A>Code</TD>
<TD><PRE>
<B>module</B> unary;
<B>reg</B> [4:0] u;
<B>initial</B> u=!'b011z;
<B>initial</B> $display("%b",u);
<B>endmodule</B></PRE>
</TD>
<TD><PRE>
<B>module</B> unary;
<B>wire</B> u;
<B>assign</B> u=!'b011z;
<B>initial</B> $display("%b",u);
<B>endmodule</B></PRE>
</TD>
<TD><PRE>
<B>module</B> unary;
<B>wire</B> u;
<B>assign</B> u=!'b011z;
<B>initial</B> #1 $display("%b",u);
<B>endmodule</B></PRE>
</TD>
<TD><PRE>
<B>module</B> unary;
<B>wire</B> u;
<B>assign</B> u=&'b1;
<B>initial</B> #1 $display("%b",u);
<B>endmodule</B></PRE>
</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=200777"></A>Output</TD>
<TD><PRE>
0000x</PRE>
</TD>
<TD><PRE>
z</PRE>
</TD>
<TD><PRE>
x</PRE>
</TD>
<TD><PRE>
0</PRE>
</TD></TR>
</TABLE>
<P CLASS="ExerciseHead"><A NAME="pgfId=200880"></A>11.22 (Unary reduction,
10 min.) Complete Table 11.18 (see next page).</P>
<P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
<TR>
<TH COLSPAN="7"><P CLASS="TableTitle"><A NAME="pgfId=200797"></A>TABLE 11.18 Unary
reduction (Problem 11.22).</TH></TR>
<TR>
<TH><P CLASS="Table"><A NAME="pgfId=200811"></A><EM>Operand</EM></TH>
<TH><P CLASS="Table"><A NAME="pgfId=200813"></A><CODE>&</CODE></TH>
<TH><P CLASS="Table"><A NAME="pgfId=200815"></A><CODE>~&</CODE></TH>
<TH><P CLASS="Table"><A NAME="pgfId=200817"></A><CODE>|</CODE></TH>
<TH><P CLASS="Table"><A NAME="pgfId=200819"></A><CODE>~|</CODE></TH>
<TH><P CLASS="Table"><A NAME="pgfId=200821"></A><CODE>^</CODE></TH>
<TH><P CLASS="Table"><A NAME="pgfId=200823"></A><CODE>~^</CODE></TH></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=200825"></A><CODE>4'b0000</CODE></TD>
<TD><P CLASS="Table"><A NAME="pgfId=200827"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=200829"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=200831"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=200833"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=200835"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=200837"></A> </TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=200839"></A><CODE>4'b1111</CODE></TD>
<TD><P CLASS="Table"><A NAME="pgfId=200841"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=200843"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=200845"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=200847"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=200849"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=200851"></A> </TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=200853"></A><CODE>4'b01x0</CODE></TD>
<TD><P CLASS="Table"><A NAME="pgfId=200855"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=200857"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=200859"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=200861"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=200863"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=200865"></A> </TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=200867"></A><CODE>4'bz000</CODE></TD>
<TD><P CLASS="Table"><A NAME="pgfId=200869"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=200871"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=200873"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=200875"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=200877"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=200879"></A> </TD></TR>
</TABLE>
<P CLASS="ExerciseHead"><A NAME="pgfId=52350"></A>11.23 (Coerced ports,
20 min.) Perform some experiments to test the behavior of your Verilog simulator
in the following situation: "NOTE--A port that is declared as input
(output) but used as an output (input) or inout may be coerced to inout.
If not coerced to inout, a warning must be issued" [Verilog LRM 12.3.6].</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=52015"></A>11.24 (*Difficult
delay code, 20 min.) Perform some experiments to explain what this difficult
to interpret statement does:</P>
<PRE>
#2 a <= <B>repeat</B>(2) @(<B>posedge</B> clk) d;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=52348"></A>11.25 (Fork-join,
20 min.) Write some test code to compare the behavior of the code fragments
shown in Table 11.19.</P>
<P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
<TR>
<TD COLSPAN="5"><P CLASS="TableTitle"><A NAME="pgfId=124747"></A>TABLE 11.19 Fork-and-join
examples for Problem 11.25.</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=66401"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=66403"></A>(a)</TD>
<TD><P CLASS="Table"><A NAME="pgfId=66405"></A>(b)</TD>
<TD><P CLASS="Table"><A NAME="pgfId=66407"></A>(c)</TD>
<TD><P CLASS="Table"><A NAME="pgfId=66409"></A>(d)</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=66411"></A>Code fragment</TD>
<TD><PRE>
<B>fork </B>
a = b;
b = a;
<B>join </B></PRE>
</TD>
<TD><PRE>
<B>fork </B>
a <= b;
b <= a;
<B>join </B></PRE>
</TD>
<TD><PRE>
<B>fork </B>
#1 a = b;
#1 b = a;
<B>join </B></PRE>
</TD>
<TD><PRE>
<B>fork</B>
a = #1 b;
b = #1 a;
<B>join</B></PRE>
</TD></TR>
</TABLE>
<P CLASS="ExerciseHead"><A NAME="pgfId=59644"></A>11.26 (Blocking and
nonblocking assignments, 20 min.) Simulate the following code and explain
the results:</P>
<PRE>
<B>module</B> nonblocking; <B>reg</B> Y;
<B> always</B> <B>begin</B> Y <= #10 1;Y <= #20 0;#10; <B>end</B>
<B> always</B> <B>begin</B> $display($time,,"Y=",Y); #10; <B>end</B>
<B> initial</B> #100 $finish;
<B>endmodule</B></PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=184473"></A>11.27 (*Flip-flop
code, 10 min.) Explain why this flip-flop does not work:</P>
<PRE>
<B>module</B> Dff_Res_Bad(D,Q,Clock,Reset);
<B>output</B> Q; <B>input</B> D,Clock,Reset; <B>reg</B> Q; <B>wire</B> D;
<B>always</B> @(<B>posedge</B> Clock) <B>if</B> (Reset !== 1) Q = D; <B>always</B> <B>if </B>(Reset == 1) Q = 0;
<B>end</B> <B>endmodule</B></PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=161581"></A>11.28 (D flip-flop,
10 min.) Test the following D flip-flop model:</P>
<PRE>
<B>module</B> DFF (D, Q, Clk, Rst);
<B>parameter</B> width = 1, reset_value = 0;
<B>input</B> [width-1:0] D; <B>output</B> [width-1:0] Q; <B>reg</B> [width-1:0] Q;
<B>input</B> Clk,Rst;
<B>initial</B> Q = {width{1'bx}};
<B>always</B> @ ( <B>posedge</B> Clk <B>or</B> <B>negedge</B> Rst )
<B>if</B> ( Rst == 0 ) Q <= #1 reset_value; <B>else</B> Q <= #1 D;
<B>endmodule</B></PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=161602"></A>11.29 (D flip-flop
with scan, 10 min.) Explain the following model:</P>
<PRE>
<B>module</B> DFFSCAN (D, Q, Clk, Rst, ScEn, ScIn, ScOut);
<B>parameter</B> width = 1, reset_value = 0;
<B>input</B> [width-1:0] D; <B>output</B> [width-1:0] Q; <B>reg</B> [width-1:0] Q;
<B>input</B> Clk,Rst,ScEn,ScIn; <B>output</B> ScOut;
<B>initial</B> Q = {width{1'bx}};
<B>always</B> @ ( <B>posedge</B> Clk <B>or</B> <B>negedge</B> Rst ) <B>begin</B>
<B>if</B> ( Rst == 0 ) Q <= #1 reset_value;
<B>else</B> <B>if</B> (ScEn) Q <= #1 {Q,ScIn};
<B>else</B> Q <= #1 D;
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