ch11.15.htm
来自「介绍asci设计的一本书」· HTM 代码 · 共 1,065 行 · 第 1/4 页
HTM
1,065 行
<HTML>
<HEAD>
<META NAME="GENERATOR" CONTENT="Adobe PageMill 2.0 Mac">
<TITLE> 11.15 Problems</TITLE>
</HEAD><!--#include file="top.html"--><!--#include file="header.html"--><br><!--#include file="AmazonAsic.html"-->
<P><A NAME="pgfId=124609"></A><HR ALIGN="LEFT"></P>
<P><A HREF="CH11.htm">Chapter start</A></P>
<P><A HREF="CH11.14.htm">Previous page</A></P>
<P><A HREF="CH11.16.htm">Next page</A></P>
<H1>11.15 Problems</H1>
<P><P CLASS="Exercise"><A NAME="pgfId=163488"></A>* = Difficult, ** = Very
difficult, *** = Extremely difficult</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=124610"></A>11.1 (Counter,
30 min.) Download the VeriWell simulator from <CODE>http://www. wellspring.com</CODE>
and simulate the counter from Section 11.1 (exclude the comments to
save typing). Include the complete input and output listings in your report.</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=137054"></A>11.2 (Simulator,
30 min.) Build a "cheat sheet" for your simulator, listing the
commands for running the simulator and using it in interactive mode.</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=124650"></A>11.3 (Verilog
examples, 10 min.) The Cadence Verilog-XL simulator comes with a directory
<CODE>examples</CODE> . Make a list of the examples from the <CODE>README</CODE>
files in the various directories.</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=163262"></A>11.4 (Gotchas,
60 min.) Build a "most common Verilog mistakes" file. Start with:</P>
<UL>
<LI><A NAME="pgfId=124617"></A>Extra or missing semicolon ';'
<LI><A NAME="pgfId=124618"></A>Forgetting to declare a <CODE>reg</CODE>
<LI><A NAME="pgfId=124619"></A>Using a <CODE>reg</CODE> instead of a <CODE>wire</CODE>
for an <CODE>input</CODE> or <CODE>inout</CODE> port
<LI><A NAME="pgfId=124620"></A>Bad declarations: <CODE>reg bus[0:31]</CODE>
instead of <CODE>reg [31:0]bus</CODE>
<LI><A NAME="pgfId=124621"></A>Mixing vector declarations:<CODE> wire [31:0]BusA,
[15:0]BusB</CODE>
<LI><A NAME="pgfId=124622"></A>The case-sensitivity of Verilog
<LI><A NAME="pgfId=124623"></A>No delay in an <CODE>always</CODE> statement
(simulator loops forever)
<LI><A NAME="pgfId=124624"></A>Mixing up <CODE>`</CODE> (accent grave)
for <CODE>`define</CODE> and <CODE>'</CODE> (tick or apostrophe) for <CODE>1'b1</CODE>
with <CODE>´</CODE> (accent acute) or <CODE>`</CODE> (open single
quote) or <CODE>'</CODE> (close single quote)
<LI><A NAME="pgfId=124625"></A>Mixing <CODE>"</CODE> <CODE>(</CODE>
double quote) with <CODE>"</CODE> (open quotes) or <CODE>"</CODE>
(close quotes)
</UL>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=124611"></A>11.5 (Sensitivity,
10 min.) Explore and explain what happens if you write this:</P>
<PRE>
<B>always </B>@(a <B>or</B> b <B>or</B> c) e = (a|b)&(c|d);</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=100848"></A>11.6 (Verilog
<CODE>if</CODE> statement, 10 min.) Build test code to simulate the following
Verilog fragment. Explain what is wrong and fix the problem.</P>
<PRE>
<B>if</B> (i > 0)
<B>if</B> (i < 2) $display ("i is 1");
<B>else</B> $display ("i is less than 0");</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=6674"></A>11.7 (Effect of
delay, 30 min.). Write code to test the four different code fragments shown
in Table 11.14 and print the value of <CODE>'a'</CODE> at time = 0
and time = 1 for each case. Explain the differences in your simulation results.</P>
<P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
<TR>
<TD COLSPAN="5"><P CLASS="TableTitle"><A NAME="pgfId=173301"></A>TABLE 11.14 Code
fragments for Problem 11.7.</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=173311"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=173313"></A>(a)</TD>
<TD><P CLASS="Table"><A NAME="pgfId=173315"></A>(b)</TD>
<TD><P CLASS="Table"><A NAME="pgfId=173317"></A>(c)</TD>
<TD><P CLASS="Table"><A NAME="pgfId=173319"></A>(d)</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=173321"></A>Code fragment</TD>
<TD><PRE>
<B>reg</B> a;
<B>initial</B>
<B>begin</B>
a = 0;
a = a + 1;
<B>end</B></PRE>
</TD>
<TD><PRE>
<B>reg</B> a;
<B>initial</B>
<B>begin</B>
#0 a = 0;
#0 a = a + 1;
<B>end</B></PRE>
</TD>
<TD><PRE>
<B>reg</B> a;
<B>initial</B>
<B>begin</B>
a <= 0;
a <= a + 1;
<B>end</B></PRE>
</TD>
<TD><PRE>
<B>reg</B> a;
<B>initial</B>
<B>begin</B>
#1 a = 0;
#1 a = a + 1;
<B>end</B></PRE>
</TD></TR>
</TABLE>
<P CLASS="ExerciseHead"><A NAME="pgfId=4806"></A>11.8 (Verilog events,
10 min.). Simulate the following and explain the results:</P>
<PRE>
<B>event</B> event_1, event_2;
<B>always</B> @ event_1 -> event_2;
<B>initial</B> @event_2 $stop;
<B>initial</B> -> event_1;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=77367"></A>11.9 (Blocking
and nonblocking assignment statements, 30 min.). Write code to test the
different code fragments shown in Table 11.15 and print the value of
<CODE>'outp'</CODE> at time = 0 and time = 10 for each case. Explain the
difference in simulation results.</P>
<P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
<TR>
<TD COLSPAN="5"><P CLASS="TableTitle"><A NAME="pgfId=77374"></A>TABLE 11.15 Code
fragments for Problem 11.9.</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=77387"></A> </TD>
<TD><P CLASS="Table"><A NAME="pgfId=77389"></A>(a)</TD>
<TD><P CLASS="Table"><A NAME="pgfId=77391"></A>(b)</TD>
<TD><P CLASS="Table"><A NAME="pgfId=77393"></A>(c)</TD>
<TD><P CLASS="Table"><A NAME="pgfId=77395"></A>(d)</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=77397"></A>Code fragment</TD>
<TD><PRE>
<B>reg</B> outp;
<B>always</B>
<B>begin</B>
#10 outp = 0;
#10 outp = 1;
<B>end</B></PRE>
</TD>
<TD><PRE>
<B>reg</B> outp;
<B>always</B>
<B>begin</B>
outp <= #10 1;
outp <= #10 0;
<B>end</B></PRE>
</TD>
<TD><PRE>
<B>reg</B> outp;
<B>always</B>
<B>begin</B>
#10 outp = 0;
#10 outp <= 1;
<B>end</B></PRE>
</TD>
<TD><PRE>
<B>reg</B> outp;
<B>always</B>
<B>begin</B>
#10 outp <= 0;
#10 outp = 1;
<B>end</B></PRE>
</TD></TR>
</TABLE>
<P CLASS="ExerciseHead"><A NAME="pgfId=6201"></A>11.10 (Verilog UDPs,
20 min.). Use this primitive to build a half adder:</P>
<PRE>
<B>primitive</B> Adder(Sum, InA, InB); <B>output</B> Sum; <B>input</B> Ina, InB;
<B>table</B> 00 : 0; 01 : 1; 10 : 1; 11 : 0; <B>endtable</B>
<B>endprimitive</B></PRE>
<P><P CLASS="Exercise"><A NAME="pgfId=9023"></A>Apply unknowns to the inputs.
What is the output?</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=6216"></A>11.11 (Verilog
UDPs, 30 min.). Use the following primitive model for a D latch:</P>
<PRE>
<B>primitive</B> DLatch(Q, Clock, Data); <B>output</B> Q; <B>reg</B> Q; <B>input</B> Clock, Data;
<B>table </B>1 0 : ? : 0; 1 1 : ? : 1; 0 1 : ? : -; <B>endtable</B>
<B>endprimitive</B></PRE>
<P><P CLASS="Exercise"><A NAME="pgfId=124522"></A>Check to see what happens
when you apply unknown inputs (including clock transitions to unknown).
What happens if you apply high-impedance values to the inputs (again including
transitions)?</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=6274"></A>11.12 (Propagation
of unknowns in primitives, 45 min.) Use the following primitive model for
a D flip-flop:</P>
<PRE>
<B>primitive</B> DFF(Q, Clock, Data); <B>output</B> Q; <B>reg</B> Q; <B>input</B> Clock, Data;
<B>table</B>
r 0 : ? : 0 ;
r 1 : ? : 1 ;
(0x) 0 : 0 : 0 ;
(0x) 1 : 1 : 1 ;
(?0) ? : ? : - ;
? (??) : ? : - ;
<B>endtable</B>
<B>endprimitive</B></PRE>
<P><P CLASS="Exercise"><A NAME="pgfId=99578"></A>Check to see what happens
when you apply unknown inputs (including a clock transition to an unknown
value). What happens if you apply high-impedance values to the inputs (again
including transitions)?</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=11710"></A>11.13 (D flip-flop
UDP, 60 min.) Table 11.16 shows a UDP for a D flip-flop with QN output
and asynchronous reset and set.</P>
<P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
<TR>
<TH><P CLASS="TableTitle"><A NAME="pgfId=124485"></A>TABLE 11.16 D
flip-flop UDP for Problem 11.13.</TH></TR>
<TR>
<TD><PRE>
<B>primitive</B> DFlipFlop2(QN, Data, Clock, Res, Set);
<B>output</B> QN; <B>reg</B> QN; <B>input</B> Data, Clock, Res, Set;
<B>table</B>
// Data Clock Res Set :state :next state
1 (01) 0 0 :? :0; // line 1
1 (01) 0 x :? :0;
? ? 0 x :0 :0;
0 (01) 0 0 :? :1;
0 (01) x 0 :? :1;
? ? x 0 :1 :1;
1 (x1) 0 0 :0 :0;
0 (x1) 0 0 :1 :1;
1 (0x) 0 0 :0 :0;
0 (0x) 0 0 :1 :1;
? ? 1 ? :? :1;
? ? 0 1 :? :0;
? n 0 0 :? :-;
* ? ? ? :? :-;
? ? (?0) ? :? :-;
? ? ? (?0) :? :-;
? ? ? ? :? :x; // line 17
<B>endtable</B>
<B>endprimitive</B></PRE>
</TD></TR>
</TABLE>
<P CLASS="ExercisePartFirst"><A NAME="pgfId=11717"></A>a. Explain the
purpose of each line in the truth table.</P>
<P><P CLASS="ExercisePart"><A NAME="pgfId=99584"></A>b. Write a module
to test each line of the UDP.</P>
<P><P CLASS="ExercisePart"><A NAME="pgfId=99585"></A>c. Can you find
any errors, omissions, or other problems in this UDP?</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=124751"></A>11.14 (JK flip-flop,
30 min.) Test the following model for a JK flip-flop:</P>
<PRE>
<B>module</B> JKFF (Q, J, K, Clk, Rst);
<B>parameter</B> width = 1, reset_value = 0;
<B>input</B> [width-1:0] J, K; <B>output</B> [width-1:0] Q; <B>reg</B> [width-1:0] Q;
<B>input</B> Clk, Rst; <B>initial</B> Q = {width{1'bx}};
<B>always</B> @ (<B>posedge</B> Clk or <B>negedge</B> Rst )
<B>if</B> (Rst==0 ) Q <= #1 reset_value;
<B>else</B> Q <= #1 (J & ~K) | (J & K & ~Q) | (~J & ~K & Q);
<B>endmodule</B></PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=5877"></A>11.15 (Overriding
Verilog parameters, 20 min.) The following module has a parameter specification
that allows you to change the number of AND gates that it models (the cardinality
or width):</P>
<PRE>
<B>module</B> Vector_AND(Z, A, B);
<B>parameter</B> card = 2; <B>input</B> [card-1:0] A,B; <B>output</B> [card-1:0] Z;
<B>wire </B>[card-1:0]<B> </B>Z = A & B;
<B>endmodule</B></PRE>
<P><P CLASS="Exercise"><A NAME="pgfId=5917"></A>The next module changes
the parameter value by specifying an overriding value in the module instantiation:</P>
<PRE>
<B>module</B> Four_AND_Gates(OutBus, InBusA, InBusB);
<B>input</B> [3:0] InBusA, InBusB; <B>output</B> [3:0] OutBus;
Vector_AND #(4) My_AND(OutBus, InBusA, InBusB);
<B>endmodule</B></PRE>
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?