ch11.htm
来自「介绍asci设计的一本书」· HTM 代码 · 共 81 行
HTM
81 行
<HTML>
<HEAD>
<META NAME="GENERATOR" CONTENT="Adobe PageMill 2.0 Mac">
<TITLE>ASICs Chapter 11: Verilog HDL </TITLE>
</HEAD><!--#include file="top.html"--><!--#include file="header.html"--><br><!--#include file="AmazonAsic.html"-->
<P><A NAME="pgfId=200898"></A><A HREF="../../ASICs.htm#anchor749424">Back
to index of chapters</A></P>
<H3>CHAPTER 11<BR>
VERILOG HDL</H3>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=66189"></A>In this chapter we
look at the <B>Verilog</B> hardware description language. Gateway Design
Automation developed Verilog as a simulation language. The use of the Verilog-XL
simulator is discussed in more detail in Chapter 13. Cadence purchased Gateway
in 1989 and, after some study, placed the Verilog language in the public
domain. Open Verilog International (OVI) was created to develop the Verilog
language as an IEEE standard. The definitive reference guide to the Verilog
language is now the Verilog LRM, IEEE Std 1364-1995 [1995]. <A HREF="#pgfId=200903" CLASS="footnote">1</A> This does not mean that all Verilog simulators and
tools adhere strictly to the IEEE Standard--we must abide by the reference
manual for the software we are using. Verilog is a fairly simple language
to learn, especially if you are familiar with the C programming language.
In this chapter we shall concentrate on the features of Verilog applied
to high-level design entry and synthesis for ASICs.</P>
<P> </P>
<P><A HREF="CH11.01.htm#pgfId=2971" CLASS="Hypertext">11.1 A
Counter</A></P>
<P><A HREF="CH11.02.htm#pgfId=12099" CLASS="Hypertext">11.2 Basics
of the Verilog Language</A></P>
<P><A HREF="CH11.03.htm#pgfId=138948" CLASS="Hypertext">11.3 Operators</A></P>
<P><A HREF="CH11.04.htm#pgfId=71115" CLASS="Hypertext">11.4 Hierarchy</A></P>
<P><A HREF="CH11.05.htm#pgfId=6800" CLASS="Hypertext">11.5 Procedures
and Assignments</A></P>
<P><A HREF="CH11.06.htm#pgfId=990" CLASS="Hypertext">11.6 Timing
Controls and Delay</A></P>
<P><A HREF="CH11.07.htm#pgfId=1058" CLASS="Hypertext">11.7 Tasks
and Functions</A></P>
<P><A HREF="CH11.08.htm#pgfId=84716" CLASS="Hypertext">11.8 Control
Statements</A></P>
<P><A HREF="CH11.09.htm#pgfId=3231" CLASS="Hypertext">11.9 Logic-Gate
Modeling</A></P>
<P><A HREF="CH11.10.htm#pgfId=10748" CLASS="Hypertext">11.10 Modeling
Delay</A></P>
<P><A HREF="CH11.11.htm#pgfId=137295" CLASS="Hypertext">11.11 Altering
Parameters</A></P>
<P><A HREF="CH11.12.htm#pgfId=5203" CLASS="Hypertext">11.12 A
Viterbi Decoder</A></P>
<P><A HREF="CH11.13.htm#pgfId=69130" CLASS="Hypertext">11.13 Other
Verilog Features</A></P>
<P><A HREF="CH11.14.htm#pgfId=7368" CLASS="Hypertext">11.14 Summary</A></P>
<P><A HREF="CH11.15.htm#pgfId=124609" CLASS="Hypertext">11.15 Problems</A></P>
<P><A HREF="CH11.16.htm#pgfId=184444" CLASS="Hypertext">11.16 Bibliography</A></P>
<P><A HREF="CH11.17.htm#pgfId=184436" CLASS="Hypertext">11.17 References</A></P>
<P><HR ALIGN="LEFT"><P CLASS="Footnote2">1. <A NAME="pgfId=200903"></A>Some
of the material in this chapter is reprinted with permission from IEEE Std
1364-1995, © Copyright 1995 IEEE. All rights reserved.
</BODY>
<!--#include file="Copyright.html"--><!--#include file="footer.html"-->
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?