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<H1>11.3 Operators</H1>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=2732"></A>An expression uses
any of the three types of operators: unary operators, binary operators,
and a single ternary operator [<A HREF="../../Verilog/LRM/HTML/04/ch04.1.htm">Verilog
LRM 4.1</A>]. The Verilog operators are similar to those in the C programming
language--except there is no autoincrement (<CODE> ++</CODE> ) or autodecrement (<CODE>
--</CODE> ) in Verilog. <A HREF="#pgfId=82149">Table 11.1</A> shows
the operators in their (increasing) order of precedence and <A HREF="#pgfId=60781">Table 11.2
</A>shows the unary operators. Here is an example that illustrates the use
of the Verilog operators:</P>
<P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
<TR>
<TD><P CLASS="TableTitle"><A NAME="pgfId=82149"></A>TABLE 11.1 Verilog
operators (in increasing order of precedence).</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=82151"></A>?: (conditional) [legal for
real; associates right to left (others associate left to right)]</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=82153"></A>|| (logical or) [A smaller
operand is zero-filled from its msb (0-fill); legal for real]</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=82155"></A>&& (logical and)[0-fill,
legal for real]</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=82157"></A>| (bitwise or) ~| (bitwise
nor) [0-fill]</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=82257"></A>^ (bitwise xor) ^~ ~^
(bitwise xnor, equivalence) [0-fill]</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=82159"></A>& (bitwise and) ~&
(bitwise nand) [0-fill]</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=82161"></A>== (logical) != (logical)
=== (case) !== (case) [0-fill, logical versions are legal for real]</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=82163"></A>< (lt) <= (lt or equal)
> (gt) >= (gt or equal) [0-fill, all arelegal for real]</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=82165"></A><< (shift left) >>
(shift right) [zero fill; no -ve shifts; shift by x or z results in unknown]</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=82167"></A>+ (addition) - (subtraction)
[if any bit is x or z for + - * / % then entire result is unknown]</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=82169"></A>* (multiply) / (divide) %
(modulus) [integer divide truncates fraction; + - * / legal for real]</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=82171"></A>Unary operators: ! ~ & ~& | ~| ^ ~^ ^~ + -
[see <A HREF="#pgfId=60781">Table 11.2 </A>for precedence]</TD></TR>
</TABLE>
<TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
<TR>
<TD COLSPAN="3"><P CLASS="TableTitle"><A NAME="pgfId=60781"></A>TABLE 11.2 Verilog
unary operators.</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=60783"></A><B>Operator</B></TD>
<TD><P CLASS="Table"><A NAME="pgfId=82027"></A><B>Name</B></TD>
<TD><P CLASS="Table"><A NAME="pgfId=82089"></A><B>Examples</B></TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=82718"></A>!</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=82720"></A>logical negation</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=82722"></A>!123 is 'b0 [0, 1, or x for
ambiguous; legal for real]</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=60785"></A>~</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=82029"></A>bitwise unary negation</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=82091"></A>~1'b10xz is 1'b01xx</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=60787"></A>&</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=82031"></A>unary reduction and</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=82093"></A>& 4'b1111 is 1'b1, &
2'bx1 is 1'bx, & 2'bz1 is 1'bx</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=60789"></A>~&</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=82033"></A>unary reduction nand</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=82095"></A>~& 4'b1111 is 1'b0, ~&
2'bx1 is 1'bx</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=60791"></A>|</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=82035"></A>unary reduction or</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=82097"></A> Note:</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=60793"></A>~|</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=82037"></A>unary reduction nor</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=82099"></A> Reduction is performed
left (first bit) to right</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=60795"></A>^</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=82039"></A>unary reduction xor</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=82101"></A> Beware of the non-associative
reduction operators</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=60797"></A>~^ ^~</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=82041"></A>unary reduction xnor</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=82103"></A> z is treated as x for
all unary operators</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=60799"></A>+</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=82043"></A>unary plus</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=82105"></A>+2'bxz is +2'bxz [+m is the
same as m; legal for real]</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=60801"></A>-</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=82045"></A>unary minus</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=82107"></A>-2'bxz is x [-m is unary
minus m; legal for real]</TD></TR>
</TABLE>
</P>
<PRE>
<B>module</B> operators;
<B>parameter</B> A10xz = {1'b1,1'b0,1'bx,1'bz}; // Concatenation and
<B>parameter</B> A01010101 = {4{2'b01}}; // replication, illegal for real.
// Arithmetic operators: +, -, *, /, and modulus %
<B>parameter</B> A1 = (3+2) %2; // The sign of a % b is the same as sign of a.
// Logical shift operators: << (left), >> (right)
<B>parameter</B> A2 = 4 >> 1; <B>parameter</B> A4 = 1 << 2; // Note: zero fill.
// Relational operators: <, <=, >, >=
<B>initial</B> <B>if</B> (1 > 2) $stop;
// Logical operators: ! (negation), && (and), || (or)
<B>parameter</B> B0 = !12; <B>parameter</B> B1 = 1 && 2;
<B>reg</B> [2:0] A00x; <B>initial</B> <B>begin</B> A00x = 'b111; A00x = !2'bx1; <B>end</B>
<B>parameter</B> C1 = 1 || (1/0); /* This may or may not cause an
error: the short-circuit behavior of && and || is undefined. An
evaluation including && or || may stop when an expression is known
to be true or false. */
// == (logical equality), != (logical inequality)
<B>parameter</B> Ax = (1==1'bx); <B>parameter</B> Bx = (1'bx!=1'bz);
<B>parameter</B> D0 = (1==0); <B>parameter</B> D1 = (1==1);
// === case equality, !== (case inequality)
// The case operators only return true (1) or false (0).
<B>parameter</B> E0 = (1===1'bx); <B>parameter</B> E1 = 4'b01xz === 4'b01xz;
<B>parameter</B> F1 = (4'bxxxx === 4'bxxxx);
// Bitwise logical operators:
// ~ (negation), & (and), | (inclusive or),
// ^ (exclusive or), ~^ or ^~ (equivalence)
<B>parameter</B> A00 = 2'b01 & 2'b10;
// Unary logical reduction operators:
// & (and), ~& (nand), | (or), ~| (nor),
// ^ (xor), ~^ or ^~ (xnor)
<B>parameter</B> G1= & 4'b1111;
// Conditional expression f = a ? b : c [if (a) then f=b else f=c]
// if a=(x or z), then (bitwise) f=0 if b=c=0, f=1 if b=c=1, else f=x
<B>reg</B> H0, a, b, c; <B>initial</B> <B>begin</B> a=1; b=0; c=1; H0=a?b:c; <B>end</B>
<B>reg</B>[2:0] J01x, Jxxx, J01z, J011;
<B>initial</B> <B>begin</B> Jxxx = 3'bxxx; J01z = 3'b01z; J011 = 3'b011;
J01x = Jxxx ? J01z : J011; <B>end</B> // A bitwise result.
<B>initial</B> <B>begin</B> #1;
$display("A10xz=%b",A10xz," A01010101=%b",A01010101);
$display("A1=%0d",A1," A2=%0d",A2," A4=%0d",A4);
$display("B1=%b",B1," B0=%b",B0," A00x=%b",A00x);
$display("C1=%b",C1," Ax=%b",Ax," Bx=%b",Bx);
$display("D0=%b",D0," D1=%b",D1);
$display("E0=%b",E0," E1=%b",E1," F1=%b",F1);
$display("A00=%b",A00," G1=%b",G1," H0=%b",H0);
$display("J01x=%b",J01x); <B>end</B>
<B>endmodule</B>
A10xz=10xz A01010101=01010101
A1=1 A2=2 A4=4
B1=1 B0=0 A00x=00x
C1=1 Ax=x Bx=x
D0=0 D1=1
E0=0 E1=1 F1=1
A00=00 G1=1 H0=0
J01x=01x</PRE>
<H2><A NAME="pgfId=166848"></A>11.3.1 Arithmetic</H2>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=3153"></A>Arithmetic operations
on n-bit objects are performed modulo 2<SUP CLASS="Superscript">n</SUP>
in Verilog,</P>
<PRE>
<B>module</B> modulo; <B>reg</B> [2:0] Seven;
<B>initial begin</B>
#1 Seven = 7; #1 $display("Before=", Seven);
#1 Seven = Seven + 1; #1 $display("After =", Seven);
<B>end</B>
<B>endmodule</B>
Before=7
After =0</PRE>
<P><P CLASS="Body"><A NAME="pgfId=181634"></A>Arithmetic operations in Verilog
(addition, subtraction, comparison, and so on) on vectors (<CODE> reg</CODE>
or <CODE>wire</CODE> ) are predefined (Tables <A HREF="#pgfId=82149">11.1</A>
and <A HREF="#pgfId=60781">11.2 </A>show which operators are legal for <CODE>real</CODE>
). This is a very important difference for ASIC designers from the situation
in VHDL. However, there are some subtleties with Verilog arithmetic and
negative numbers that are illustrated by the following example (based on
an example in the LRM [<A HREF="../../Verilog/LRM/HTML/04/ch04.1.htm">Verilog LRM4.1</A>]):</P>
<PRE>
<B>module</B> LRM_arithmetic;
<B>integer</B> IA, IB, IC, ID, IE; <B>reg</B> [15:0] RA, RB, RC;
<B>initial</B> <B>begin</B>
IA = -4'd12; RA = IA / 3; // reg is treated as unsigned.
RB = -4'd12; IB = RB / 3; //
IC = -4'd12 / 3; RC = -12 / 3; // real is treated as signed
ID = -12 / 3; IE = IA / 3; // (two's complement).
<B>end</B>
<B>initial</B> <B>begin</B> #1;
$display(" hex default");
$display("IA = -4'd12 = %h%d",IA,IA);
$display("RA = IA / 3 = %h %d",RA,RA);
$display("RB = -4'd12 = %h %d",RB,RB);
$display("IB = RB / 3 = %h%d",IB,IB);
$display("IC = -4'd12 / 3 = %h%d",IC,IC);
$display("RC = -12 / 3 = %h %d",RC,RC);
$display("ID = -12 / 3 = %h%d",ID,ID);
$display("IE = IA / 3 = %h%d",IE,IE);
<B>end</B>
<B>endmodule</B>
hex default
IA = -4'd12 = fffffff4 -12
RA = IA / 3 = fffc 65532
RB = -4'd12 = fff4 65524
IB = RB / 3 = 00005551 21841
IC = -4'd12 / 3 = 55555551 1431655761
RC = -12 / 3 = fffc 65532
ID = -12 / 3 = fffffffc -4
IE = IA / 3 = fffffffc -4</PRE>
<P><P CLASS="Body"><A NAME="pgfId=175231"></A>We might expect the results
of all these divisions to be - 4 = -12/3. For integer assignments, the results
are correctly signed (<CODE> ID</CODE> and <CODE>IE</CODE> ). Hex <CODE>fffc</CODE>
(decimal 65532) is the 16-bit two's complement of - 4, so <CODE>RA</CODE>
and <CODE>RC</CODE> are also correct if we keep track of the signs ourselves.
The integer result <CODE>IB</CODE> is incorrect because Verilog treats <CODE>RB</CODE>
as an unsigned number. Verilog also treats <CODE>-4'd12 </CODE>as an unsigned
number in the calculation of <CODE>IC</CODE> . Once Verilog "loses"
a sign, it cannot get it back (see also Section <A HREF="CH11.02.htm#pgfId=166691">11.2.5</A>).</P>
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