ch11.13.htm
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`timescale 100 fs / 1 fs
<B>module</B> dff(q, clock, data); <B>output</B> q; <B>input</B> clock, data; <B>reg</B> notifier;
dff_udp(q1, clock, data, notifier); buf(q, q1);
<B>specify</B>
<B>specparam</B> tSU = 5, tH = 1, tPW = 20, tPLH = 4:5:6, tPHL = 4:5:6;
(clock *> q) = (tPLH, tPHL);
$setup(data, <B>posedge</B> clock, tSU, notifier); // setup: data to clock
$hold(<B>posedge</B> clock, data, tH, notifier); // hold: clock to data
$period(<B>posedge</B> clock, tPW, notifier); // clock: period
<B>endspecify</B>
<B>endmodule</B></PRE>
<H2><A NAME="pgfId=173821"></A>11.13.4 PLA Tasks</H2>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=173823"></A>The <B>PLA modeling
tasks</B> model two-level logic [Verilog LRM 14.6]. As an example, the following
<CODE>eqntott</CODE> logic equations can be implemented using a PLA:</P>
<PRE>
b1 = a1 & a2; b2 = a3 & a4 & a5 ; b3 = a5 & a6 & a7;</PRE>
<P><P CLASS="Body"><A NAME="pgfId=123094"></A>The following module loads
a PLA model for the equations above (in AND logic) using the <B>array format</B>
(the array format allows only <CODE>'1'</CODE> or <CODE>'0'</CODE> in the
PLA memory, or <B>personality array</B>). The file <CODE>array.dat</CODE>
is similar to the <CODE>espresso</CODE> input plane format.</P>
<PRE>
array.dat
1100000
0011100
0000111
<B>module</B> pla_1 (a1,a2,a3,a4,a5,a6,a7,b1,b2,b3);
<B>input</B> a1, a2, a3, a4, a5, a6, a7 ; output b1, b2, b3;
<B>reg</B> [1:7] mem[1:3]; <B>reg</B> b1, b2, b3;
<B>initial</B> <B>begin</B>
$readmemb("array.dat", mem);
#1; b1=1; b2=1; b3=1;
$async$and$array(mem,{a1,a2,a3,a4,a5,a6,a7},{b1,b2,b3});
<B>end</B>
<B>initial</B> $monitor("%4g",$time,,b1,,b2,,b3);
<B>endmodule</B></PRE>
<P><P CLASS="Body"><A NAME="pgfId=161467"></A>The next example illustrates
the use of the <B>plane format</B>, which allows <CODE>'1'</CODE> , <CODE>'0'</CODE>
, as well as <CODE>'?'</CODE> or <CODE>'z'</CODE> (either may be used for
don't care) in the personality array.</P>
<PRE>
b1 = a1 & !a2; b2 = a3; b3 = !a1 & !a3; b4 = 1;
<B>module</B> pla_2; <B>reg</B> [1:3] a, mem[1:4]; <B>reg</B> [1:4] b;
<B>initial</B> <B>begin</B>
$async$and$plane(mem,{a[1],a[2],a[3]},{b[1],b[2],b[3],b[4]});
mem[1] = 3'b10?; mem[2] = 3'b??1; mem[3] = 3'b0?0; mem[4] = 3'b???;
#10 a = 3'b111; #10 $displayb(a, " -> ", b);
#10 a = 3'b000; #10 $displayb(a, " -> ", b);
#10 a = 3'bxxx; #10 $displayb(a, " -> ", b);
#10 a = 3'b101; #10 $displayb(a, " -> ", b);
<B>end</B> <B>endmodule</B>
111 -> 0101
000 -> 0011
xxx -> xxx1
101 -> 1101</PRE>
<H2><A NAME="pgfId=123203"></A>11.13.5 Stochastic Analysis
Tasks</H2>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=125074"></A>The <B>stochastic
analysis tasks</B> model queues [Verilog LRM 14.7]. Each of the tasks return
a status as shown in Table 11.12.</P>
<P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
<TR>
<TH COLSPAN="2"><P CLASS="TableTitle"><A NAME="pgfId=123356"></A>TABLE 11.12 Status
values for the stochastic analysis tasks.</TH></TR>
<TR>
<TH><P CLASS="Table"><A NAME="pgfId=123317"></A><B>Status value</B></TH>
<TH><P CLASS="Table"><A NAME="pgfId=123319"></A><B>Meaning</B></TH></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=123321"></A>0</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=123323"></A>OK</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=123325"></A>1</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=123327"></A>queue full, cannot add</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=123329"></A>2</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=123331"></A>undefined <CODE>q_id</CODE></TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=123333"></A>3</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=123335"></A>queue empty, cannot remove</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=123337"></A>4</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=123339"></A>unsupported <CODE>q_type</CODE>
, cannot create queue</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=123341"></A>5</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=123343"></A><CODE>max_length</CODE>
<= 0, cannot create queue</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=123345"></A>6</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=123347"></A>duplicate <CODE>q_id</CODE>
, cannot create queue</TD></TR>
<TR>
<TD><P CLASS="Table"><A NAME="pgfId=123349"></A>7</TD>
<TD><P CLASS="TableLeft"><A NAME="pgfId=123351"></A>not enough memory, cannot
create queue</TD></TR>
</TABLE>
<P CLASS="Body"><A NAME="pgfId=70466"></A>The following module illustrates
the interface and parameters for these tasks:</P>
<PRE>
<B>module</B> stochastic; <B>initial</B> <B>begin </B>// stochastic analysis system tasks:
/* $q_initialize (q_id, q_type, max_length, status) ;
q_id is an integer that uniquely identifies the queue
q_type 1=FIFO 2=LIFO
max_length is an integer defining the maximum number of entries */
$q_initialize (q_id, q_type, max_length, status) ;
/* $q_add (q_id, job_id, inform_id, status) ;
job_id = integer input
inform_id = user-defined integer input for queue entry */
$q_add (q_id, job_id, inform_id, status) ;
/* $q_remove (q_id, job_id, inform_id, status) ; */
$q_remove (q_id, job_id, inform_id, status) ;
/* $q_full (q_id, status) ;
status = 0 = queue is not full, status = 1 = queue full */
$q_full (q_id, status) ;
/* $q_exam (q_id, q_stat_code, q_stat_value, status) ;
q_stat_code is input request as follows:
1=current queue length 2=mean inter-arrival time 3=max. queue length
4=shortest wait time ever
5=longest wait time for jobs still in queue 6=ave. wait time in queue
q_stat_value is output containing requested value */
$q_exam (q_id, q_stat_code, q_stat_value, status) ;
<B>end</B> <B>endmodule</B></PRE>
<H2><A NAME="pgfId=121060"></A>11.13.6 Simulation Time
Functions</H2>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=125075"></A>The <B>simulation
time functions</B> return the time as follows [Verilog LRM 14.8]:</P>
<PRE>
<B>module</B> test_time; <B>initial</B> <B>begin</B> // simulation time system functions:
$time ;
// returns 64-bit integer scaled to timescale unit of invoking module
$stime ;
// returns 32-bit integer scaled to timescale unit of invoking module
$realtime ;
// returns real scaled to timescale unit of invoking module
<B>end</B> <B>endmodule</B></PRE>
<H2><A NAME="pgfId=121064"></A>11.13.7 <B> Conversion
Functions</B></H2>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=125076"></A>The <B>conversion
functions for reals</B> handle real numbers [Verilog LRM 14.9]:</P>
<PRE>
<B>module</B> test_convert; // conversion functions for reals:
<B>integer</B> i; <B>real</B> r; <B>reg</B> [63:0] bits;
<B>initial</B> begin #1 r=256;#1 i = $rtoi(r);
#1; r = $itor(2 * i) ; #1 bits = $realtobits(2.0 * r) ;
#1; r = $bitstoreal(bits) ; <B>end</B>
<B>initial</B> $monitor("%3f",$time,,i,,r,,bits); /*
$rtoi converts reals to integers w/truncation e.g. 123.45 -> 123
$itor converts integers to reals e.g. 123 -> 123.0
$realtobits converts reals to 64-bit vector
$bitstoreal converts bit pattern to real
Real numbers in these functions conform to IEEE Std 754. Conversion rounds to the nearest valid number. */
<B>endmodule</B>
# 0.000000 x 0 x
# 1.000000 x 256 x
# 2.000000 256 256 x
# 3.000000 256 512 x
# 4.000000 256 512 4652218415073722368
# 5.000000 256 1024 4652218415073722368</PRE>
<P><P CLASS="Body"><A NAME="pgfId=121055"></A>Here is an example using the
conversion functions in port connections:</P>
<PRE>
<B>module</B> test_real;<B>wire</B> [63:0]a; driver d (a); receiver r (a);
<B>initial</B> $monitor("%3g",$time,,a,,d.r1,,r.r2);<B> endmodule</B>
<B>module</B> driver (real_net);
<B>output</B> real_net; <B>real</B> r1; <B>wire</B> [64:1] real_net = $realtobits(r1);
<B>initial</B> #1 r1 = 123.456; <B>endmodule</B>
<B>module</B> receiver (real_net);
<B>input</B> real_net; <B>wire</B> [64:1] real_net; <B>real</B> r2;
<B>initial</B> <B>assign</B> r2 = $bitstoreal(real_net);
<B>endmodule</B>
# 0 0 0 0
# 1 4638387860618067575 123.456 123.456</PRE>
<H2><A NAME="pgfId=123846"></A>11.13.8 Probability Distribution
Functions</H2>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=136873"></A>The probability distribution
functions are as follows [Verilog LRM 14.10]:</P>
<PRE>
<B>module</B> probability; // probability distribution functions:
/* $random [ ( seed ) ] returns random 32-bit signed integer
seed = register, integer, or time */
<B>reg</B> [23:0] r1,r2; integer r3,r4,r5,r6,r7,r8,r9;
<B>integer</B> seed, start, \end , mean, standard_deviation;
<B>integer</B> degree_of_freedom, k_stage;
initial begin seed=1; start=0; \end =6; mean=5;
standard_deviation=2; degree_of_freedom=2; k_stage=1; #1;
r1 = $random % 60; // random -59 to 59
r2 = {$random} % 60; // positive value 0-59
r3=$dist_uniform (seed, start, \end ) ;
r4=$dist_normal (seed, mean, standard_deviation) ;
r5=$dist_exponential (seed, mean) ;
r6=$dist_poisson (seed, mean) ;
r7=$dist_chi_square (seed, degree_of_freedom) ;
r8=$dist_t (seed, degree_of_freedom) ;
r9=$dist_erlang (seed, k_stage, mean) ; end
initial #2 $display ("%3f",$time,,r1,,r2,,r3,,r4,,r5);
initial begin #3; $display ("%3f",$time,,r6,,r7,,r8,,r9); end
/* All parameters are integer values.
Each function returns a pseudo-random number
e.g. $dist_uniform returns uniformly distributed random numbers
mean, degree_of_freedom, k_stage
(exponential, poisson, chi-square, t, erlang) > 0.
seed = inout integer initialized by user, updated by function
start, end ($dist_uniform) = integer bounding return values */
<B>endmodule</B>
2.000000 8 57 0 4 9
3.000000 7 3 0 2</PRE>
<H2><A NAME="pgfId=124346"></A>11.13.9 Programming Language
Interface</H2>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=105654"></A>The C language <B>Programming
Language Interface</B> (<B> PLI</B>) allows you to access the internal Verilog
data structure [Verilog LRM17-23, A-E]. For example, you can use
the PLI to implement the following extensions to a Verilog simulator:</P>
<UL>
<LI><A NAME="pgfId=69160"></A>C language delay calculator for a cell library
<LI><A NAME="pgfId=69161"></A>C language interface to a Verilog-based or
other logic or fault simulator
<LI><A NAME="pgfId=69162"></A>Graphical waveform display and debugging
<LI><A NAME="pgfId=69164"></A>C language simulation models
<LI><A NAME="pgfId=69165"></A>Hardware interfaces
</UL>
<P><P CLASS="Body"><A NAME="pgfId=69166"></A>There are three generations
of PLI routines (see Appendix B for an example):</P>
<UL>
<LI><A NAME="pgfId=69167"></A>Task/function (TF) routines (or utility routines),
the first generation of the PLI, start with<CODE> 'tf_'</CODE> .
<LI><A NAME="pgfId=69168"></A>Access (ACC) routines, the second generation
of the PLI, start with the characters <CODE>'acc_'</CODE> and access delay
and logic values. There is some overlap between the ACC routines and TF
routines.
<LI><A NAME="pgfId=69169"></A>Verilog Procedural Interface (VPI) routines,
the third generation of the PLI, start with the characters <CODE>'vpi_'</CODE>
and are a superset of the TF and ACC routines.
</UL>
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