ch11.12.htm
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<TD><P CLASS="Table"><A NAME="pgfId=149057"></A>1</TD>
<TD><P CLASS="Table"><A NAME="pgfId=149059"></A>S<SUB CLASS="Subscript">1</SUB></TD>
<TD><P CLASS="Table"><A NAME="pgfId=149061"></A>S<SUB CLASS="Subscript">2</SUB></TD>
<TD><P CLASS="Table"><A NAME="pgfId=149063"></A>1</TD>
<TD><P CLASS="Table"><A NAME="pgfId=149065"></A>0</TD>
<TD><P CLASS="Table"><A NAME="pgfId=149067"></A>1</TD>
<TD><P CLASS="Table"><A NAME="pgfId=149069"></A>4</TD>
<TD><P CLASS="Table"><A NAME="pgfId=149071"></A>6</TD>
<TD><P CLASS="Table"><A NAME="pgfId=149073"></A>7</TD>
<TD><P CLASS="Table"><A NAME="pgfId=149075"></A>6</TD>
<TD><P CLASS="Table"><A NAME="pgfId=149077"></A>4</TD></TR>
<TR>
<TD><P CLASS="TableLeft"><A NAME="pgfId=149079"></A>950</TD>
<TD><P CLASS="Table"><A NAME="pgfId=149081"></A>1</TD>
<TD><P CLASS="Table"><A NAME="pgfId=149083"></A>0</TD>
<TD><P CLASS="Table"><A NAME="pgfId=149085"></A>S<SUB CLASS="Subscript">2</SUB></TD>
<TD><P CLASS="Table"><A NAME="pgfId=149087"></A>S<SUB CLASS="Subscript">1</SUB></TD>
<TD><P CLASS="Table"><A NAME="pgfId=149089"></A>0</TD>
<TD><P CLASS="Table"><A NAME="pgfId=149091"></A>1</TD>
<TD><P CLASS="Table"><A NAME="pgfId=149093"></A>4</TD>
<TD><P CLASS="Table"><A NAME="pgfId=149095"></A>6</TD>
<TD><P CLASS="Table"><A NAME="pgfId=149097"></A>7</TD>
<TD><P CLASS="Table"><A NAME="pgfId=149099"></A>6</TD>
<TD><P CLASS="Table"><A NAME="pgfId=149101"></A>4</TD>
<TD><P CLASS="Table"><A NAME="pgfId=149103"></A>1</TD></TR>
</TABLE>
</P>
<H2><A NAME="pgfId=149105"></A>11.12.3 Testing the System</H2>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=150449"></A>Here is a testbench
for the entire system: encoder, receiver front end, and decoder:</P>
<PRE>
/*****************************************************/
/* module viterbi_test_CDD */
/*****************************************************/
/* This is the top-level module, viterbi_test_CDD, that models the
communications link. It contains three modules: viterbi_encode,
viterbi_distances, and viterbi. There is no analog and no noise in
this version. The 2-bit message, X, is encoded to a 3-bit signal, Y.
In this module the message X is generated using a simple counter.
The digital 3-bit signal Y is transmitted, received with noise as an
analog signal (not modeled here), and converted to a set of eight
3-bit distance measures, in0, ..., in7. The distance measures form
the input to the Viterbi decoder that reconstructs the transmitted
signal Y, with an error signal if the measures are inconsistent.
CDD = counter input, digital transmission, digital reception */
<B>module</B> viterbi_test_CDD;
<B>wire</B> Error; // decoder out
<B>wire</B> [2:0] Y, Out; // encoder out, decoder out
<B>reg</B> [1:0] X; // encoder inputs
<B>reg</B> Clk, Res; // clock and reset
<B>wire</B> [2:0] in0,in1,in2,in3,in4,in5,in6,in7;
<B>always</B> #500 $display("t Clk X Y Out Error");
<B>initial</B> $monitor("%4g",$time,,Clk,,,,X,,Y,,Out,,,,Error);
<B>initial </B>$dumpvars; <B>initial</B> #3000 $finish;
<B>always</B> #50 Clk = ~Clk; <B>initial</B> <B>begin</B> Clk = 0;
X = 3; // No special reason to start at 3.
#60 Res = 1;#10 Res = 0; <B>end</B> // Hit reset after inputs are stable.
<B>always</B> @(<B>posedge</B> Clk) #1 X = X + 1; // Drive the input with a counter.
viterbi_encode v_1
(X[1],X[0],Y[2],Y[1],Y[0],Clk,Res);
viterbi_distances v_2
(Y[2],Y[1],Y[0],Clk,Res,in0,in1,in2,in3,in4,in5,in6,in7);
viterbi v_3
(in0,in1,in2,in3,in4,in5,in6,in7,Out,Clk,Res,Error);
<B>endmodule</B></PRE>
<P><P CLASS="Body"><A NAME="pgfId=150627"></A>The Viterbi decoder takes
the distance measures and calculates the most likely transmitted signal.
It does this by keeping a running history of the previously received signals
in a path memory. The path-memory length of this decoder is 12. By keeping
a history of possible sequences and using the knowledge that the signals
were generated by a state machine, it is possible to select the most likely
sequences.</P>
<P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
<TR>
<TH COLSPAN="2"><P CLASS="TableTitle"><A NAME="pgfId=150914"></A>TABLE 11.10 Output
from the Viterbi testbench</TH></TR>
<TR>
<TD><PRE>
t Clk X Y Out Error
0 0 3 x x 0
50 1 3 x x 0
51 1 0 x x 0
60 1 0 0 0 0
100 0 0 0 0 0
150 1 0 0 0 0
151 1 1 2 0 0</PRE>
</TD>
<TD><PRE>
t Clk X Y Out Error
1351 1 1 0 0 0
1400 0 1 0 0 0
1450 1 1 0 0 0
1451 1 2 5 2 0
1500 0 2 5 2 0
1550 1 2 5 2 0
1551 1 3 4 5 0</PRE>
</TD></TR>
</TABLE>
<P CLASS="Body"><A NAME="pgfId=151113"></A>Table 11.10 shows part of
the simulation results from the testbench, viterbi_test_CDD, in tabular
form. Figure 11.5 shows the Verilog simulator output from the testbench
(displayed using VeriWell from Wellspring).</P>
<P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
<TR>
<TD><P CLASS="TableFigure"><A NAME="pgfId=151123"></A><IMG SRC="CH11-69.gif" ALIGN="BASELINE" WIDTH="454" HEIGHT="132" NATURALSIZEFLAG="3"> </TD></TR>
<TR>
<TD><P><P CLASS="TableFigure"><A NAME="pgfId=151129"></A> </P>
<P><IMG SRC="CH11-70.gif" WIDTH="455" HEIGHT="124" NATURALSIZEFLAG="3" ALIGN="BOTTOM"></TD></TR>
<TR>
<TD><P CLASS="TableFigureTitle"><A NAME="pgfId=200707"></A>FIGURE 11.5 Viterbi
encoder testbench simulation results. (Top) Initialization and the
start of the encoder output sequence 2, 5, 4, 1, 0, ... on Y[2:0] at t<B>
</B>= 151. (Bottom) The appearance of the same encoder output sequence
at the output of the decoder, Out[2:0], at t<B> </B>= 1451, 1300 time units
(13 positive clock edges) later.</TD></TR>
</TABLE>
<P CLASS="Body"><A NAME="pgfId=150648"></A>The system input or message,
<CODE>X[1:0]</CODE> , is driven by a counter that repeats the sequence 0, 1, 2, 3, ...
incrementing by 1 at each positive clock edge (with a delay of one time
unit), starting with <CODE>X</CODE> equal to 3 at t<B> </B>= 0. The active-high
reset signal, <CODE>Res</CODE> , is asserted at t = 60 for 10 time units.
The encoder output, <CODE>Y[2:0]</CODE> , changes at t = 151, which is one
time unit (the positive-edge-triggered D flip-flop model contains a one-time-unit
delay) after the first positive clock edge (at t = 150) following the deassertion
of the reset at t = 70. The encoder output sequence beginning at t<B> </B>=
151 is 2, 5, 4, 1, 0, ... and then the sequence
5, 4, 1, 0, ... repeats. This encoder output sequence
is then imagined to be transmitted and received. The receiver module calculates
the distance measures and passes them to the decoder. After 13 positive
clock-edges (1300 time ticks) the transmitted sequence appears at the output,
<CODE>Out[2:0]</CODE> , beginning at t = 1451 with 2, 5, 4, 1, 0, ...,
exactly the same as the encoder output.</P>
<H2><A NAME="pgfId=100830"></A>11.12.4 Verilog Decoder
Model</H2>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=129754"></A>The Viterbi decoder
model presented in this section is written for both simulation and synthesis.
The Viterbi decoder makes extensive use of vector D flip-flops (registers).
Early versions of Verilog-XL did not support vector instantiations of modules.
In addition the inputs of UDPs may not be vectors and there are no primitive
D flip-flops in Verilog. This makes instantiation of a register difficult
other than by writing a separate module instance for each flip-flop.</P>
<P><P CLASS="Body"><A NAME="pgfId=163747"></A>The first solution to this
problem is to use flip-flop models supplied with the synthesis tool such
as the following:</P>
<PRE>
asDff #(3) subout0(in0, sub0, clk, reset);</PRE>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=7544"></A>The asDff is a model
in the Compass ASIC Synthesizer standard component library. This statement
triggers the synthesis of three D flip-flops, with an input vector <CODE>ina</CODE>
(with a range of three) connected to the D inputs, an output vector <CODE>sub0</CODE>
(also with a range of three) connected to the Q flip-flop outputs, a common
scalar clock signal, <CODE>clk</CODE> , and a common scalar <CODE>reset</CODE>
signal. The disadvantage of this approach is that the names, functional
behavior, and interfaces of the standard components are different for every
software system.</P>
<P><P CLASS="Body"><A NAME="pgfId=132864"></A>The second solution, in new
versions of Verilog-XL and other tools that support the IEEE standard, is
to use vector instantiation as follows [LRM 7.5.1, 12.1.2]:</P>
<PRE>
myDff subout0[0:2] (in0, sub0, clk, reset);</PRE>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=132840"></A>This instantiates
three copies of a user-defined module or UDP called my<CODE> Dff</CODE>
. The disadvantage of this approach is that not all simulators and synthesizers
support vector instantiation.</P>
<P><P CLASS="Body"><A NAME="pgfId=163771"></A>The third solution (which
is used in the Viterbi decoder model) is to write a model that supports
vector inputs and outputs. Here is an example D flip-flop model:</P>
<PRE>
/******************************************************/
/* module dff */
/******************************************************/
/* A D flip-flop module. */
<B>module</B> dff(D,Q,Clock,Reset); // N.B. reset is active-low.
<B>output</B> Q; <B>input</B> D,Clock,Reset;
<B>parameter</B> CARDINALITY = 1; <B>reg</B> [CARDINALITY-1:0] Q;
<B>wire</B> [CARDINALITY-1:0] D;
<B>always</B> @(<B>posedge</B> Clock) <B>if</B> (Reset !== 0) #1 Q = D;
<B>always</B> <B>begin</B> <B>wait</B> (Reset == 0); Q = 0; <B>wait</B> (Reset == 1); <B>end</B>
<B>endmodule</B></PRE>
<P><P CLASS="Body"><A NAME="pgfId=152341"></A>We use this model by defining
a parameter that specifies the bus width as follows:</P>
<P><P CLASS="Body"><A NAME="pgfId=163773"></A>dff #(3) subout0(in0, sub0,
clk, reset);</P>
<P><P CLASS="Body"><A NAME="pgfId=163780"></A>The code that models the entire
Viterbi decoder is listed below (Figure 12.6 on page 578 shows the block
digram). Notice the following:</P>
<UL>
<LI><A NAME="pgfId=152354"></A>Comments explain the function of each module.
<LI><A NAME="pgfId=152356"></A>Each module is about a page or less of code.
<LI><A NAME="pgfId=152357"></A>Each module can be tested by itself.
<LI><A NAME="pgfId=152358"></A>The code is as simple as possible avoiding
clever coding techniques.
</UL>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=152361"></A>The code is not flexible,
because bit widths are fixed rather than using parameters. A model with
parameters for rate, signal constellation, distance measure resolution,
and path memory length is considerably more complex. We shall use this Viterbi
decoder design again when we discuss logic synthesis in Chapter 12, test
in Chapter 14, floorplanning and placement in Chapter 16, and routing in
Chapter 17.</P>
<PRE>
/* Verilog code for a Viterbi decoder. The decoder assumes a rate
2/3 encoder, 8 PSK modulation, and trellis coding. The viterbi module
contains eight submodules: subset_decode, metric, compute_metric,
compare_select, reduce, pathin, path_memory, and output_decision.
The decoder accepts eight 3-bit measures of ||r-si||**2 and, after
an initial delay of thirteen clock cycles, the output is the best
estimate of the signal transmitted. The distance measures are the
Euclidean distances between the received signal r (with noise) and
each of the (in this case eight) possible transmitted signals s0 to s7.
Original by Christeen Gray, University of Hawaii. Heavily modified
by MJSS; any errors are mine. Use freely. */
/******************************************************/
/* module viterbi */
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