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  <TITLE> 11.7&nbsp;&nbsp;&nbsp;Tasks and Functions</TITLE>

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<H1>11.7&nbsp;&nbsp;&nbsp;Tasks and Functions</H1>

<P><P CLASS="BodyAfterHead"><A NAME="pgfId=1064"></A>A <B>task</B> [Verilog

LRM&nbsp;10.2] is a type of procedure, called from another procedure. A

task has both inputs and outputs but does not return a value. A task may

call other tasks and functions. A <B>function</B> [Verilog LRM&nbsp;10.3]

is a procedure used in any expression, has at least one input, no outputs,

and returns a single value. A function may not call a task. In Section&nbsp;11.5

we covered all of the different Verilog procedures except for tasks and

functions. Now that we have covered timing controls, we can explain the

difference between tasks and functions: Tasks may contain timing controls

but functions may not. The following two statements help illustrate the

difference between a function and a task:</P>

<PRE>

Call_A_Task_And_Wait (Input1, Input2, Output);

Result_Immediate = Call_A_Function (All_Inputs);</PRE>

<P><P CLASS="Body"><A NAME="pgfId=84698"></A>Functions are useful to model

combinational logic (rather like a subroutine):</P>

<PRE>

<B>module</B> F_subset_decode; <B>reg</B> [2:0]A, B, C, D, E, F;

<B>initial</B> <B>begin</B> A = 1; B = 0; D = 2; E = 3;

&nbsp;&nbsp;C = subset_decode(A, B); F = subset_decode(D,E);

&nbsp;&nbsp;$display(&quot;A B C D E F&quot;); $display(A,,B,,C,,D,,E,,F); <B>end</B>

<B>function</B> [2:0] subset_decode; <B>input</B> [2:0] a, b;

&nbsp;&nbsp;<B>begin</B> <B>if </B>(a &lt;= b) subset_decode = a; <B>else</B> subset_decode = b; <B>end</B>

<B>endfunction</B> 

<B>endmodule</B>

A B C D E F

1 0 0 2 3 2</PRE>

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