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<H1>11.11 Altering Parameters</H1>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=5772"></A>Here is an example
of a module that uses a parameter [Verilog LRM3.10, 12.2]:</P>
<PRE>
<B>module</B> Vector_And(Z, A, B);
<B>parameter</B> CARDINALITY = 1;
<B>input</B> [CARDINALITY-1:0] A, B;
<B> output</B> [CARDINALITY-1:0] Z;
<B>wire </B>[CARDINALITY-1:0]<B> </B>Z = A & B;
<B>endmodule</B></PRE>
<P><P CLASS="Body"><A NAME="pgfId=6312"></A>We can override this parameter
when we instantiate the module as follows:</P>
<PRE>
<B>module</B> Four_And_Gates(OutBus, InBusA, InBusB);
<B>input</B> [3:0] InBusA, InBusB; <B>output</B> [3:0] OutBus;
Vector_And #(4) My_AND(OutBus, InBusA, InBusB); // 4 AND gates
<B>endmodule</B></PRE>
<P><P CLASS="Body"><A NAME="pgfId=5805"></A>The parameters of a module have
local scope, but we may override them using a <B>defparam</B> statement
and a hierarchical name, as in the following example:</P>
<PRE>
<B>module</B> And_Gates(OutBus, InBusA, InBusB);
<B>parameter</B> WIDTH = 1;
<B>input</B> [WIDTH-1:0] InBusA, InBusB; <B>output</B> [WIDTH-1:0] OutBus;
Vector_And #(WIDTH) My_And(OutBus, InBusA, InBusB);
<B>endmodule</B>
<B>module</B> Super_Size; <B>defparam </B>And_Gates.WIDTH = 4; <B>endmodule</B></PRE>
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