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<H1>11.10 Modeling Delay</H1>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=11101"></A>Verilog has a set
of built-in methods to define delays. This is very important in ASIC physical
design. Before we start layout, we can use ASIC cell library models written
in Verilog that include logic delays as a function of fanout and estimated
wiring loads. After we have completed layout, we can extract the wiring
capacitance, allowing us to calculate the exact delay values. Using the
techniques described in this section, we can then back-annotate our Verilog
netlist with postlayout delays and complete a postlayout simulation.</P>
<P><P CLASS="Body"><A NAME="pgfId=11124"></A>We can complete this back-annotation
process in a standard fashion since delay specification is part of the Verilog
language. This makes working with an ASIC cell library and the ASIC foundry
that will fabricate our ASIC much easier. Typically an ASIC library company
might sell us a cell library complete with Verilog models that include all
the minimum, typical, and maximum delays as well as the different values
for rising and falling transitions. The ASIC foundry will provide us with
a delay calculator that calculates the net delays (this is usually proprietary
technology) from the layout. These delays are held in a separate file (the
<B>Standard Delay Format</B>, <B>SDF</B>, is widely used) and then mapped
to parameters in the Verilog models. If we complete back-annotation and
a postlayout simulation using an approved cell library, the ASIC foundry
will "sign off" on our design. This is basically a guarantee that
our chip will work according to the simulation. This ability to design sign-off
quality ASIC cell libraries is very important in the ASIC design process.</P>
<H2><A NAME="pgfId=10761"></A>11.10.1 Net and Gate Delay</H2>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=11001"></A>We saw how to specify
a delay control for any statement in <A HREF="CH11.06.htm">Section 11.6</A>.
In fact, Verilog allows us to specify minimum, typical, and maximum values
for the delay as follows [Verilog LRM7.15]:</P>
<PRE>
#(1.1:1.3:1.7) <B>assign</B> delay_a = a; // min:typ:max</PRE>
<P><P CLASS="Body"><A NAME="pgfId=10809"></A>We can also specify the delay
properties of a<CODE> wire </CODE>in a similar fashion:</P>
<PRE>
<B>wire</B> #(1.1:1.3:1.7) a_delay; // min:typ:max</PRE>
<P><P CLASS="Body"><A NAME="pgfId=10949"></A>We can specify delay in a <CODE>wire</CODE>
declaration together with a continuous assignment as in the following example:</P>
<PRE>
<B>wire</B> #(1.1:1.3:1.7) a_delay = a; // min:typ:max</PRE>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=77260"></A>but in this case the
delay is associated with the driver and not with the<CODE> wire</CODE> .</P>
<P><P CLASS="Body"><A NAME="pgfId=137012"></A>In <A HREF="CH11.09.htm#pgfId=5204">Section 11.9.1</A>
we explained that we can specify a delay for a logic primitive. We can also
specify minimum, typical, and maximum delays as well as separate delays
for rising and falling transitions for primitives as follows [<A HREF="../../Verilog/LRM/HTML/04/ch04.3.htm">Verilog
LRM4.3</A>]:</P>
<PRE>
nand #3.0 nd01(c, a, b);
nand #(2.6:3.0:3.4) nd02(d, a, b); // min:typ:max
nand #(2.8:3.2:3.4, 2.6:2.8:2.9) nd03(e, a, b);
// #(rising, falling) delay</PRE>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=10781"></A>The first NAND gate,
<CODE>nd01</CODE> , has a delay of 3 ns (assuming we specified nanoseconds
as the timescale) for both rising and falling delays. The NAND gate <CODE>nd02</CODE>
has a triplet for the delay; this corresponds to a minimum (2.6 ns), typical
(3.0 ns), and a maximum delay (3.4 ns). The NAND gate <CODE>nd03</CODE>
has two triplets for the delay: The first triplet specifies the min/typ/max
rising delay (<CODE> '0'</CODE> or <CODE>'x'</CODE> or <CODE>'z'</CODE>
to <CODE>'1'</CODE> ), and the second triplet specifies the min/typ/max
falling delay (<CODE> '1'</CODE> or <CODE>'x'</CODE> or <CODE>'z'</CODE>
to <CODE>'0'</CODE> ).</P>
<P><P CLASS="Body"><A NAME="pgfId=10977"></A>Some primitives can produce
a high-impedance output, <CODE>'z'</CODE> . In this case we can specify
a triplet of delay values corresponding to rising transition, falling transition,
and the delay to transition to <CODE>'z'</CODE> (from <CODE>'0'</CODE> or
<CODE>'1'</CODE> to <CODE>'z'</CODE> --this is usually the delay for a three-state
driver to turn off or float). We can do the same thing for net types,</P>
<PRE>
<B>wire</B> #(0.5,0.6,0.7) a_z = a; // rise/fall/float delays</PRE>
<H2><A NAME="pgfId=209094"></A>11.10.2 Pin-to-Pin Delay</H2>
<P><P CLASS="BodyAfterHead"><A NAME="pgfId=209097"></A>The <B>specify block</B>
[Verilog LRM 13] is a special construct in Verilog that allows the definition
of <B>pin-to-pin delays</B> across a module. The use of a specify block
can include the use of built-in system functions to check setup and hold
times, for example. The following example illustrates how to specify pin-to-pin
timing for a D flip-flop. We declare the timing parameters first followed
by the paths. This example uses the UDP from Section 11.9.2, which
does not include preset and clear (so only part of the flip-flop function
is modeled), but includes the timing for preset and clear for illustration
purposes.</P>
<PRE>
<B>module</B> DFF_Spec; <B>reg</B> D, clk;
DFF_Part DFF1 (Q, clk, D, pre, clr);
<B>initial</B> <B>begin</B> D = 0; clk = 0; #1; clk = 1; <B>end</B>
<B>initial</B> $monitor("T=%2g", $time," clk=", clk," Q=", Q);
<B>endmodule</B>
<B>module</B> DFF_Part(Q, clk, D, pre, clr);
<B>input</B> clk, D, pre, clr; <B>output</B> Q;
DFlipFlop(Q, clk, D); // No preset or clear in this UDP.
<B>specify </B>
<B>specparam</B>
tPLH_clk_Q = 3, tPHL_clk_Q = 2.9,
tPLH_set_Q = 1.2, tPHL_set_Q = 1.1;
(clk => Q) = (tPLH_clk_Q, tPHL_clk_Q);
(pre, clr *> Q) = (tPLH_set_Q, tPHL_set_Q);
<B>endspecify</B>
<B>endmodule</B>
T= 0 clk=0 Q=x
T= 1 clk=1 Q=x
T= 4 clk=1 Q=0</PRE>
<P><P CLASS="Body"><A NAME="pgfId=11085"></A>There are the following two
ways to specify paths (module<CODE> DFF_part</CODE> above uses both) [Verilog
LRM13.3]:</P>
<UL>
<LI><A NAME="pgfId=11086"></A><CODE>x => y</CODE> specifies a <B>parallel
connection</B> (or parallel path) between <CODE>x</CODE> and <CODE>y</CODE>
(<CODE> x</CODE> and <CODE>y</CODE> must have the same number of bits).
<LI><A NAME="pgfId=11093"></A><CODE>x *> y</CODE> specifies a <B>full
connection</B> (or full path) between <CODE>x</CODE> and <CODE>y</CODE>
(every bit in <CODE>x</CODE> is connected to <CODE>y)</CODE> . In this
case <CODE>x</CODE> and <CODE>y</CODE> may be different sizes.
</UL>
<P><P CLASS="Body"><A NAME="pgfId=136254"></A>The delay of some logic cells
depends on the state of the inputs. This can be modeled using a <B>state-dependent
path delay</B>. Here is an example:</P>
<PRE>
`timescale 1 ns / 100 fs
<B>module</B> M_Spec; <B>reg</B> A1, A2, B; M M1 (Z, A1, A2, B);
<B>initial</B> <B>begin</B> A1=0;A2=1;B=1;#5;B=0;#5;A1=1;A2=0;B=1;#5;B=0; <B>end</B>
<B>initial</B>
$monitor("T=%4g",$realtime," A1=",A1," A2=",A2," B=",B," Z=",Z);
<B>endmodule</B>
`timescale 100 ps / 10 fs
<B>module</B> M(Z, A1, A2, B); <B>input</B> A1, A2, B; <B>output</B> Z;
<B>or</B> (Z1, A1, A2); <B>nand</B> (Z, Z1, B); // OAI21
/*A1 A2 B Z Delay=10*100 ps unless indicated in the table below.
0 0 0 1
0 0 1 1
0 1 0 1 B:0->1 Z:1->0 delay=t2
0 1 1 0 B:1->0 Z:0->1 delay=t1
1 0 0 1 B:0->1 Z:1->0 delay=t4
1 0 1 0 B:1->0 Z:0->1 delay=t3
1 1 0 1
1 1 1 0 */
<B>specify</B> <B>specparam</B> t1 = 11, t2 = 12; <B>specparam</B> t3 = 13, t4 = 14;
(A1 => Z) = 10; (A2 => Z) = 10;
<B> if </B>(~A1) (B => Z) = (t1, t2); <B>if </B>(A1) (B => Z) = (t3, t4);
<B>endspecify</B>
<B>endmodule</B>
T= 0 A1=0 A2=1 B=1 Z=x
T= 1 A1=0 A2=1 B=1 Z=0
T= 5 A1=0 A2=1 B=0 Z=0
T= 6.1 A1=0 A2=1 B=0 Z=1
T= 10 A1=1 A2=0 B=1 Z=1
T= 11 A1=1 A2=0 B=1 Z=0
T= 15 A1=1 A2=0 B=0 Z=0
T=16.3 A1=1 A2=0 B=0 Z=1</PRE>
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