ch12.4.htm

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<LI CLASS="BulletList">

<A NAME="pgfId=252881">

 </A>

20 (5  <SPAN CLASS="Symbol">

&#165;</SPAN>

  4) D flip-flops in instance <SPAN CLASS="BodyComputer">

metric</SPAN>

</LI>

</UL>

<P CLASS="Body">

<A NAME="pgfId=252882">

 </A>

The total is 24  +  132  +  12  +  20  =  188 D flip-flops, which is the same as the number of <SPAN CLASS="BodyComputer">

dfctnb</SPAN>

 cell instances in <A HREF="#17078" CLASS="XRef">

Table&nbsp;12.7</A>

.</P>

<TABLE>

<TR>

<TD ROWSPAN="1" COLSPAN="2">

<P CLASS="TableTitle">

<A NAME="pgfId=252691">

 </A>

TABLE&nbsp;12.7&nbsp;<A NAME="17078">

 </A>

Number of synthesized flip-flops in the Viterbi ASIC.</P>

</TD>

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<P CLASS="TableFirst">

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Command </P>

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<P CLASS="TableFirst">

<A NAME="pgfId=252709">

 </A>

Synthesizer output<A HREF="#pgfId=252708" CLASS="footnote">

3</A>

</P>

</TD>

</TR>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="Computer">

<A NAME="pgfId=252718">

 </A>

&gt; report area -flat </P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="Computer">

<A NAME="pgfId=252828">

 </A>

&nbsp;</P>

<P CLASS="Computer">

<A NAME="pgfId=252829">

 </A>

                 Num    Gate Count    Tot Gate       Width       Total</P>

<P CLASS="Computer">

<A NAME="pgfId=252830">

 </A>

  Cell Name    Insts      Per Cell       Count    Per Cell       Width</P>

<P CLASS="Computer">

<A NAME="pgfId=252831">

 </A>

  ---------    -----    ----------    --------    --------    --------</P>

<P CLASS="Computer">

<A NAME="pgfId=252832">

 </A>

...</P>

<P CLASS="Computer">

<A NAME="pgfId=252834">

 </A>

  dfctnb         188           5.8      1081.0        55.2     10377.6</P>

<P CLASS="Computer">

<A NAME="pgfId=252835">

 </A>

...</P>

<P CLASS="Computer">

<A NAME="pgfId=252846">

 </A>

  ---------    -----    ----------    --------    --------    --------</P>

<P CLASS="Computer">

<A NAME="pgfId=252732">

 </A>

  Totals:       1383                   12716.5                 25485.6</P>

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</TABLE>

<P CLASS="Body">

<A NAME="pgfId=253314">

 </A>

<A HREF="#27256" CLASS="XRef">

Table&nbsp;12.6</A>

 gives the total width of the standard cells in the logic core after logic optimization as 18,048  <SPAN CLASS="Symbol">

m</SPAN>

m. Since the standard-cell height for this library is 72  <SPAN CLASS="Symbol">

l</SPAN>

 (21.6<SPAN CLASS="Symbol">

  m</SPAN>

m), we can make a first estimate of the total logic cell area as  </P>

<TABLE>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableEqn">

<A NAME="pgfId=414772">

 </A>

(18,048 <SPAN CLASS="Symbol">

m</SPAN>

m) (21.6 <SPAN CLASS="Symbol">

m</SPAN>

m)</P>

</TD>

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<SPAN CLASS="EquationVariables">

=</SPAN>

</P>

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<TD ROWSPAN="1" COLSPAN="1">

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<A NAME="pgfId=414776">

 </A>

390 k(<SPAN CLASS="Symbol">

m</SPAN>

m)<SUP CLASS="Superscript">

2</SUP>

</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableEqn">

<A NAME="pgfId=414908">

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&nbsp;</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

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(12.12)</P>

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<A NAME="pgfId=414781">

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&nbsp;</P>

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<A NAME="pgfId=414783">

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&nbsp;</P>

</TD>

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<SUP CLASS="Superscript">

</SUP>

&nbsp;</P>

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<A NAME="pgfId=414910">

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&nbsp;</P>

</TD>

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&nbsp;</P>

</TD>

</TR>

<TR>

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&nbsp;</P>

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&nbsp;</P>

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<TD ROWSPAN="1" COLSPAN="1">

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<A NAME="pgfId=414874">

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390 k(<SPAN CLASS="Symbol">

m</SPAN>

m)<SUP CLASS="Superscript">

2</SUP>

 mil<SUP CLASS="Superscript">

2</SUP>

</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableEqn">

<A NAME="pgfId=414912">

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&nbsp;</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="Table">

<A NAME="pgfId=414861">

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&nbsp;</P>

</TD>

</TR>

<TR>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableEqn">

<A NAME="pgfId=414799">

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&nbsp;</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableEqnCenter">

<A NAME="pgfId=414801">

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<SPAN CLASS="Symbol">

&#170;</SPAN>

</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableEqnCenter">

<A NAME="pgfId=414803">

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&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;&#8211;</P>

</TD>

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&nbsp;</P>

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&nbsp;</P>

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&nbsp;</P>

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&nbsp;</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableEqnCenter">

<A NAME="pgfId=414815">

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(25.4 <SPAN CLASS="Symbol">

m</SPAN>

m)<SUP CLASS="Superscript">

2</SUP>

</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableEqn">

<A NAME="pgfId=414916">

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&nbsp;</P>

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<A NAME="pgfId=414817">

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&nbsp;</P>

</TD>

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<TR>

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<P CLASS="TableEqn">

<A NAME="pgfId=414888">

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&nbsp;</P>

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&nbsp;</P>

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<A NAME="pgfId=414892">

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&nbsp;</P>

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&nbsp;</P>

</TD>

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<A NAME="pgfId=414894">

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&nbsp;</P>

</TD>

</TR>

<TR>

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<P CLASS="TableEqn">

<A NAME="pgfId=414823">

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&nbsp;</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableEqnCenter">

<A NAME="pgfId=414825">

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<SPAN CLASS="Symbol">

&#170;</SPAN>

</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableEqnLeft">

<A NAME="pgfId=414827">

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600 mil<SUP CLASS="Superscript">

2</SUP>

</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="TableEqn">

<A NAME="pgfId=414920">

 </A>

&nbsp;</P>

</TD>

<TD ROWSPAN="1" COLSPAN="1">

<P CLASS="Table">

<A NAME="pgfId=414829">

 </A>

&nbsp;</P>

</TD>

</TR>

</TABLE>

<P CLASS="Body">

<A NAME="pgfId=253337">

 </A>

In the physical layout we shall need additional space for routing. The ratio of routing to logic cell area is called the <SPAN CLASS="Definition">

routing factor</SPAN>

<A NAME="marker=253351">

 </A>

. The routing factor depends primarily on whether we use two levels or three levels of metal. With two levels of metal the routing factor is typically between 1 and 2. With three levels of metal, where we may use over-the-cell routing, the routing factor is usually zero to 1. We thus expect a logic core area of 600&#8211;1000  mils<SUP CLASS="Superscript">

2</SUP>

 for the Viterbi decoder using this cell library. </P>

<P CLASS="Body">

<A NAME="pgfId=253533">

 </A>

From <A HREF="#27256" CLASS="XRef">

Table&nbsp;12.6</A>

 we see the I/O cells in this library are 100.8  <SPAN CLASS="Symbol">

m</SPAN>

m wide or approximately 4  mil (the width of a single pad site). From the I/O cell data book we find the I/O cell height is 650  <SPAN CLASS="Symbol">

m</SPAN>

m (actually 648.825  <SPAN CLASS="Symbol">

m</SPAN>

m) or approximately 26  mil. Each I/O cell thus occupies 104  mil<SUP CLASS="Superscript">

2</SUP>

. Our 33 pad sites will thus require approximately 3400  mil<SUP CLASS="Superscript">

2</SUP>

 which is larger than the estimated core logic area.</P>

<P CLASS="Body">

<A NAME="pgfId=264622">

 </A>

Let us go back and take a closer look at what it usually takes to get to this point. Remember we used an already prepared Verilog model for the Viterbi decoder. </P>

</DIV>

<HR>

<DIV CLASS="footnotes">

<DIV CLASS="footnote">

<P CLASS="TableFootnote">

<SPAN CLASS="footnoteNumber">

1.</SPAN>

<A NAME="pgfId=246697">

 </A>

See footnote <A HREF="CH12.2.htm#31398" CLASS="XRef">

1</A>

 in <A HREF="CH12.2.htm#23004" CLASS="XRef">

Table&nbsp;12.3</A>

 for explanations of the abbreviations used in this table.</P>

</DIV>

<DIV CLASS="footnote">

<P CLASS="TableFootLast">

<SPAN CLASS="footnoteNumber">

2.</SPAN>

<A NAME="pgfId=264841">

 </A>

I/O cell height (I/O cells have prefixes <SPAN CLASS="BodyComputer">

pc5</SPAN>

 and <SPAN CLASS="BodyComputer">

pv</SPAN>

) is approximately 650  <SPAN CLASS="Symbol">

m</SPAN>

m in this cell library.</P>

</DIV>

<DIV CLASS="footnote">

<P CLASS="TableFootLast">

<SPAN CLASS="footnoteNumber">

3.</SPAN>

<A NAME="pgfId=252708">

 </A>

See footnote <A HREF="CH12.2.htm#31398" CLASS="XRef">

1</A>

 in <A HREF="CH12.2.htm#23004" CLASS="XRef">

Table&nbsp;12.3</A>

 for explanations of the abbreviations used in this table. Logic cell dfctnb is a D flip-flop with clear in this standard-cell library.</P>

</DIV>

</DIV>

<HR><P>[&nbsp;<A HREF="CH12.htm">Chapter&nbsp;start</A>&nbsp;]&nbsp;[&nbsp;<A HREF="CH12.3.htm">Previous&nbsp;page</A>&nbsp;]&nbsp;[&nbsp;<A HREF="CH12.5.htm">Next&nbsp;page</A>&nbsp;]</P></BODY>



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