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<TITLE> 12.4 Synthesis of the Viterbi Decoder</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
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12.4 <A NAME="29176">
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Synthesis of the Viterbi Decoder</H1>
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In this section we return to the Viterbi decoder from Chapter 11. After an initial synthesis run that shows how logic synthesis works with a real example, we step back and study some of the issues and problems of using HDLs for logic synthesis.</P>
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12.4.1 ASIC I/O</H2>
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Some logic synthesizers can include I/O cells automatically, but the designer may have to use directives to designate special pads (clock buffers, for example). It may also be necessary to use commands to set I/O cell features such as selection of pull-up resistor, slew rate, and so on. Unfortunately there are no standards in this area. Worse, there is currently no accepted way to set these parameters from an HDL. Designers may also use either generic technology-independent I/O models or instantiate I/O cells directly from an I/O cell library. Thus, for example, in the Compass tools the statement</P>
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asPadIn #(3,"1,2,3") u0 (in0, padin0);</P>
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<A NAME="pgfId=284379">
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uses a generic I/O cell model, <SPAN CLASS="BodyComputer">
asPadIn</SPAN>
. This statement will generate three input pads (with pin numbers <SPAN CLASS="BodyComputer">
"1"</SPAN>
, <SPAN CLASS="BodyComputer">
"2"</SPAN>
, and <SPAN CLASS="BodyComputer">
"3"</SPAN>
) if <SPAN CLASS="BodyComputer">
in0</SPAN>
is a 3-bit-wide bus.</P>
<P CLASS="Body">
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The next example illustrates the use of generic I/O cells from a standard-component library. These components are technology independent (so they may equally well be used with a 0.6 <SPAN CLASS="Symbol">
m</SPAN>
m or 0.35 <SPAN CLASS="Symbol">
m</SPAN>
m technology).</P>
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<A NAME="pgfId=284381">
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<B CLASS="Keyword">
module</B>
allPads(padTri, padOut, clkOut, padBidir, padIn, padClk);</P>
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<A NAME="pgfId=284382">
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<B CLASS="Keyword">
output</B>
padTri, padOut, clkOut; inout padBidir;</P>
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<A NAME="pgfId=284383">
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<B CLASS="Keyword">
input</B>
[3:0] padIn; <B CLASS="Keyword">
input</B>
padClk; <B CLASS="Keyword">
wire</B>
[3:0] in;</P>
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<A NAME="pgfId=284384">
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//compass dontTouch u*</P>
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// asPadIn #(W, N, L, P) I (toCore, Pad) also asPadInInv</P>
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<A NAME="pgfId=284386">
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// asPadOut #(W, N, L, P) I (Pad, frCore)</P>
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<A NAME="pgfId=284387">
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// asPadTri #(W, N, S, L, P) I (Pad, frCore, OEN)</P>
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<A NAME="pgfId=284388">
</A>
// asPadBidir #(W, N, S, L, P) I (Pad, toCore, frCore, OEN)</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=284389">
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// asPadClk #(N, S, L) I (Clk, Pad) also asPadClkInv</P>
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<A NAME="pgfId=284390">
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// asPadVxx #(N, subnet) I (Vxx)</P>
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<A NAME="pgfId=284391">
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// W = width, integer (default=1)</P>
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<A NAME="pgfId=284392">
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// N = pin number string, e.g. "1:3,5:8" </P>
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<A NAME="pgfId=284393">
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// S = strength = {2, 4, 8, 16} in mA drive</P>
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// L = level = {cmos, ttl, schmitt} (default = cmos)</P>
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<A NAME="pgfId=284395">
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// P = pull-up resistor = {down, float, none, up} </P>
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<A NAME="pgfId=284396">
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// Vxx = {Vss, Vdd}</P>
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// subnet = connect supply to {pad, core, both} </P>
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<A NAME="pgfId=284398">
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asPadIn #(4,"1:4","","none") u1 (in, padIn);</P>
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<A NAME="pgfId=284400">
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<A NAME="42091">
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asPadOut #(1,"5",13) u2 (padOut, d);</P>
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<A NAME="pgfId=284401">
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asPadTri #(1,"6",11) u3 (padTri, in[1], in[0]);</P>
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<A NAME="pgfId=284402">
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asPadBidir #(1,"7",2,"","") u4 (d, padBidir, in[3], in[2]);</P>
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<A NAME="pgfId=284404">
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<A NAME="16055">
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asPadClk #(8) u5 (clk, padClk);</P>
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<A NAME="pgfId=284405">
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asPadOut #(1, "9") u6 (clkOut, clk);</P>
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<A NAME="pgfId=284406">
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asPadVdd #("10:11","pads") u7 (vddr);</P>
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<A NAME="pgfId=284407">
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asPadVss #("12,13","pads") u8 (vssr);</P>
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<A NAME="pgfId=284408">
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asPadVdd #("14","core") u9 (vddc);</P>
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<A NAME="pgfId=284409">
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asPadVss #("15","core") u10 (vssc);</P>
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<A NAME="pgfId=284410">
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asPadVdd #("16","both") u11 (vddb);</P>
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<A NAME="pgfId=284411">
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asPadVss #("17","both") u12 (vssb);</P>
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<A NAME="pgfId=284412">
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<B CLASS="Keyword">
endmodule</B>
</P>
<P CLASS="Body">
<A NAME="pgfId=284413">
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The following code is an example of the contents of a generic model for a three-state I/O cell (provided in a standard-component library or in an I/O cell library): </P>
<P CLASS="ComputerFirstLabelV">
<A NAME="pgfId=284414">
</A>
<B CLASS="Keyword">
module</B>
PadTri (Pad, I, Oen); // active-low output enable</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=284415">
</A>
<B CLASS="Keyword">
parameter</B>
width = 1, pinNumbers = "", \strength = 1, </P>
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<A NAME="pgfId=284416">
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level = "CMOS", externalVdd = 5;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=284417">
</A>
<B CLASS="Keyword">
output</B>
[width-1:0] Pad; <B CLASS="Keyword">
input</B>
[width-1:0] I; <B CLASS="Keyword">
input</B>
Oen;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=284418">
</A>
<B CLASS="Keyword">
assign</B>
#1 Pad = (Oen ? {width{1'bz}} : I);</P>
<P CLASS="ComputerLastLabelV">
<A NAME="pgfId=284419">
</A>
<B CLASS="Keyword">
endmodule</B>
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</P>
<P CLASS="Body">
<A NAME="pgfId=284420">
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The module <SPAN CLASS="BodyComputer">
PadTri</SPAN>
can be used for simulation and as the basis for synthesizing an I/O cell. However, the synthesizer also has to be told to synthesize an I/O cell connected to a bonding pad and the outside world and not just an internal three-state buffer. There is currently no standard mechanism for doing this, and every tool and every ASIC company handles it differently. </P>
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The following model is a generic model for a bidirectional pad. We could use this model as a basis for input-only and output-only I/O cell models.</P>
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<B CLASS="Keyword">
module</B>
PadBidir (C, Pad, I, Oen); // active-low output enable</P>
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<A NAME="pgfId=284422">
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<B CLASS="Keyword">
parameter</B>
width = 1, pinNumbers = "", \strength = 1, </P>
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level = "CMOS", pull = "none", externalVdd = 5;</P>
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<A NAME="pgfId=284424">
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<B CLASS="Keyword">
output</B>
[width-1:0] C; <B CLASS="Keyword">
inout </B>
[width-1:0] Pad;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=284425">
</A>
<B CLASS="Keyword">
input </B>
[width-1:0] I; <B CLASS="Keyword">
input</B>
Oen;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=284426">
</A>
<B CLASS="Keyword">
assign</B>
#1 Pad = Oen ? {width{1'bz}} : I; <B CLASS="Keyword">
assign</B>
#1 C = Pad;</P>
<P CLASS="ComputerLastLabelV">
<A NAME="pgfId=284427">
</A>
<B CLASS="Keyword">
endmodule</B>
</P>
<P CLASS="Body">
<A NAME="pgfId=284431">
</A>
In Chapter 8 we used the <SPAN CLASS="BodyComputer">
halfgate</SPAN>
example to demonstrate an FPGA design flow—including I/O. If the synthesis tool is not capable of synthesizing I/O cells, then we may have to instantiate them by hand; the following code is a hand-instantiated version of lines <A HREF="#42091" CLASS="XRef">
19</A>
–<A HREF="#16055" CLASS="XRef">
22</A>
in module <SPAN CLASS="BodyComputer">
allPads</SPAN>
:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=284439">
</A>
pc5o05 u2_2 (.PAD(padOut), .I(d));</P>
<P CLASS="Computer">
<A NAME="pgfId=284440">
</A>
pc5t04r u3_2 (.PAD(padTri), .I(in[1]), .OEN(in[0]));</P>
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<A NAME="pgfId=284441">
</A>
pc5b01r u4_3 (.PAD(padBidir), .I(in[3]), .CIN(d), .OEN(in[2]));</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=284442">
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pc5d01r u5_in_1 (.PAD(padClk), .CIN(u5toClkBuf[0]));</P>
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<A NAME="pgfId=284443">
</A>
The designer must find the names of the I/O cells (<SPAN CLASS="BodyComputer">
pc5o05</SPAN>
and so on), and the names, positions, meanings, and defaults for the parameters from the cell-library documentation.</P>
<P CLASS="Body">
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I/O cell models allow us to simulate the behavior of the synthesized logic inside an ASIC “all the way to the pads.” To simulate “outside the pads” at a system level, we should use these same I/O cell models. This is important in ASIC design. For example, the designers forgot to put pull-up resistors on the outputs of some of the SparcStation ASICs. This was one of the very few errors in a complex project, but an error that could have been caught if a system-level simulation had included complete I/O cell models for the ASICs.</P>
</DIV>
<DIV>
<H2 CLASS="Heading2">
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12.4.2 Flip-Flops</H2>
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In Chapter 11 we used this D flip-flop model to simulate the Viterbi decoder:</P>
<P CLASS="ComputerFirstLabelV">
<A NAME="pgfId=284449">
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<B CLASS="Keyword">
module</B>
dff(D,Q,Clock,Reset); // N.B. reset is active-low</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=284450">
</A>
<B CLASS="Keyword">
output</B>
Q; <B CLASS="Keyword">
input</B>
D,Clock,Reset;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=284451">
</A>
<B CLASS="Keyword">
parameter</B>
CARDINALITY = 1; <B CLASS="Keyword">
reg</B>
[CARDINALITY-1:0] Q;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=284452">
</A>
<B CLASS="Keyword">
wire</B>
[CARDINALITY-1:0] D;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=284453">
</A>
<B CLASS="Keyword">
always</B>
@(<B CLASS="Keyword">
posedge</B>
Clock) <B CLASS="Keyword">
if</B>
(Reset!==0) #1 Q=D;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=284454">
</A>
<B CLASS="Keyword">
always</B>
<B CLASS="Keyword">
begin</B>
<B CLASS="Keyword">
wait</B>
(Reset==0); Q=0; <B CLASS="Keyword">
wait</B>
(Reset==1); <B CLASS="Keyword">
end</B>
</P>
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<A NAME="pgfId=284455">
</A>
<B CLASS="Keyword">
endmodule</B>
<A NAME="39510">
</A>
</P>
<P CLASS="Body">
<A NAME="pgfId=284456">
</A>
Most simulators cannot synthesize this model because there are two <SPAN CLASS="BodyComputer">
wait</SPAN>
statements in one <SPAN CLASS="BodyComputer">
always</SPAN>
statement (line <A HREF="#30561" CLASS="XRef">
6</A>
). We could change the code to use flip-flops from the synthesizer standard-component library by using the following code:</P>
<P CLASS="ComputerOneLine">
<A NAME="pgfId=284457">
</A>
asDff ff1 (.Q(y), .D(x), .Clk(clk), .Rst(vdd));</P>
<P CLASS="Body">
<A NAME="pgfId=284458">
</A>
Unfortunately we would have to change all the flip-flop models from <SPAN CLASS="BodyComputer">
'dff'</SPAN>
to <SPAN CLASS="BodyComputer">
'asDff'</SPAN>
and the code would become dependent on a particular synthesis tool. Instead, to maintain independence from vendors, we shall use the following D flip-flop model for synthesis and simulation:</P>
<P CLASS="ComputerFirstLabelV">
<A NAME="pgfId=284459">
</A>
<B CLASS="Keyword">
module</B>
dff(D, Q, Clk, Rst); // new flip-flop for Viterbi decoder</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=284460">
</A>
<B CLASS="Keyword">
parameter</B>
width = 1, reset_value = 0; <B CLASS="Keyword">
input</B>
[width - 1 : 0] D;</P>
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