ch12.9.htm

介绍asci设计的一本书

TSQ</SPAN>
 (SH to Q) =0. 7  ns</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=266358">
 </A>
The next problem occurs because VHDL is not a synthesis language (from lines 6&#8211;7 of the variable-width shift register in Table&nbsp;10.7),</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=264489">
 </A>
begin assert (D'LENGTH &lt;= Q'LENGTH) </P>
<P CLASS="ComputerLast">
<A NAME="pgfId=264490">
 </A>
	report &quot;D wider than output Q&quot; severity Failure;</P>
<P CLASS="Computer">
<A NAME="pgfId=264491">
 </A>
<B CLASS="Keyword">
Warning</B>
: Assertion statements are ignored</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=264492">
 </A>
<B CLASS="Keyword">
Error</B>
: Statements in entity declarations are not supported</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=264493">
 </A>
The synthesis tool warns us it does not know how to generate hardware that writes to our screen to implement an <SPAN CLASS="BodyComputer">
assertion</SPAN>
 statement. The error occurs because a synthesis tool cannot support any of the passive statements (no assignments to signals, for example) that VHDL allows in an entity declaration. Synthesis software usually provides a way around these problems by providing switches to turn the synthesizer on and off. For example, we might be able to write the following:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=265353">
 </A>
//Compass compile_off</P>
<P CLASS="Computer">
<A NAME="pgfId=265357">
 </A>
begin assert (D'LENGTH &lt;= Q'LENGTH) </P>
<P CLASS="Computer">
<A NAME="pgfId=265363">
 </A>
	report &quot;D wider than output Q&quot; severity Failure;</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=265354">
 </A>
//Compass compile_on</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=265351">
 </A>
The disadvantage of this approach is that the code now becomes tied to a particular synthesis tool. The alternative is to move the statement to the architecture to eliminate the error, and ignore the warning.</P>
<P CLASS="Body">
<A NAME="pgfId=265036">
 </A>
The next error message is, at first sight, confusing (from lines 15&#8211;16 of the variable-width shift register in Table&nbsp;10.7),</P>
<P CLASS="ComputerOneLine">
<A NAME="pgfId=264494">
 </A>
if CLR = '1' then St := (others =&gt; '0'); Q &lt;= St after TCQ;</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=264495">
 </A>
<B CLASS="Keyword">
Error</B>
: Illegal use of aggregate with the choice &quot;others&quot;:  the derived subtype of an array aggregate that has a choice &quot;others&quot; must be a constrained array subtype</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=265081">
 </A>
This error message is precise and uses the terminology of the LRM but does not reveal the source of the problem. To discover the problem we work backward through the model. We declared variable <SPAN CLASS="BodyComputer">
St</SPAN>
 as follows (lines 12&#8211;13 of Table&nbsp;10.7):</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=265390">
 </A>
subtype OutB is NATURAL range Q'LENGTH-1 downto 0;</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=265391">
 </A>
	variable St: BIT_VECTOR(OutB);</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=265387">
 </A>
(to keep the model flexible). Continuing backward we see <SPAN CLASS="BodyComputer">
Q</SPAN>
 is declared as type <SPAN CLASS="BodyComputer">
BIT_VECTOR</SPAN>
 with no index range as follows (lines 4&#8211;5 of Table&nbsp;10.7): </P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=265557">
 </A>
port(CLK, CLR, LD, SH, DIR: in BIT; </P>
<P CLASS="ComputerLast">
<A NAME="pgfId=265559">
 </A>
		D: in BIT_VECTOR; Q: out BIT_VECTOR);</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=265555">
 </A>
The error is thus linked to the previous problem (undeclared bus widths) in this entity&#8211;architecture pair. Because the synthesizer does not know the width of <SPAN CLASS="BodyComputer">
Q</SPAN>
, it does not know how many <SPAN CLASS="BodyComputer">
'0'</SPAN>
s to put in <SPAN CLASS="BodyComputer">
St</SPAN>
 when it has to implement <SPAN CLASS="BodyComputer">
St := (others =&gt; '0')</SPAN>
. There is one more error like this one in the second assignment to <SPAN CLASS="BodyComputer">
St </SPAN>
(line 19 in Table&nbsp;10.7). Again the problem may be solved by sacrificing flexibility and constraining the width of <SPAN CLASS="BodyComputer">
Q</SPAN>
 to be a fixed value.</P>
<P CLASS="Body">
<A NAME="pgfId=265108">
 </A>
The next warning involves names (line 5 in Table&nbsp;10.9),</P>
<P CLASS="ComputerOneLine">
<A NAME="pgfId=265091">
 </A>
signal SRA, SRB, ADDout, MUXout, REGout: BIT_VECTOR(7 downto 0);</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=264498">
 </A>
<B CLASS="Keyword">
Warning</B>
: Name is reserved word in VHDL-93: sra</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=264499">
 </A>
This problem can be fixed by (a) changing the signal name, (b) using an escaped name, or (c) accepting that this code will not work in a VHDL-93 environment.</P>
<P CLASS="Body">
<A NAME="pgfId=265123">
 </A>
Finally, there is the following warning (line 6 in Table&nbsp;10.9):</P>
<P CLASS="ComputerOneLine">
<A NAME="pgfId=264500">
 </A>
signal Zero, Init, Shift, Add, Low: BIT := '0'; signal High: BIT := '1';</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=264501">
 </A>
<B CLASS="Keyword">
Warning</B>
: Initial values on signals are only for simulation and setting the value of undriven signals in synthesis.  A synthesized circuit can not be guaranteed to be in any known state when the power is turned on.</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=264502">
 </A>
Signals <SPAN CLASS="BodyComputer">
Low</SPAN>
 and <SPAN CLASS="BodyComputer">
High</SPAN>
 are used to tie inputs to a logic <SPAN CLASS="BodyComputer">
'0'</SPAN>
 and to a logic <SPAN CLASS="BodyComputer">
'1'</SPAN>
, respectively. This is because VHDL-87 does not allow <SPAN CLASS="BodyComputer">
'1'</SPAN>
 or <SPAN CLASS="BodyComputer">
'0'</SPAN>
, which are <A NAME="marker=395363">
 </A>
literals, as actual parameters. Thus one way to solve this problem is to change to a VHDL-93 environment, where this restriction was lifted. Some synthesis systems handle VDD and GND nets in a specific fashion. For example, VDD and GND may be declared as constants in a synthesis package. It does not really matter how inputs are connected to VDD and GND as long as they are connected in the synthesized logic.</P>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=264503">
 </A>
12.9.1&nbsp;Messages During Synthesis</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=265659">
 </A>
After fixing the error and warning messages, we can synthesize the multiplier. During synthesis we see these messages:</P>
<P CLASS="ComputerOneLine">
<A NAME="pgfId=264504">
 </A>
These unused instances are being removed: in full_adder_p_dup8: u5, u2, u3, u4</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=264505">
 </A>
These unused instances are being removed: in dffclr_p_dup1: u2</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=264506">
 </A>
and seven more similar to this for <SPAN CLASS="BodyComputer">
dffclr_p_dup2: u2</SPAN>
 to <SPAN CLASS="BodyComputer">
dffclr_p_dup8: u2</SPAN>
.<SPAN CLASS="BodyComputer">
 </SPAN>
We are suspicious because we did not include any <A NAME="marker=395364">
 </A>
redundant or unused logic in our input code. Let us dig deeper.</P>
<P CLASS="Body">
<A NAME="pgfId=265517">
 </A>
Turning to the second set of messages first, we need to discover the locations of <SPAN CLASS="BodyComputer">
dffclr_p_dup1: u2</SPAN>
 and the other seven similarly named unused instances. We can ask the synthesizer to produce the following hierarchy map of the design:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=264508">
 </A>
*************  Hierarchy of cell &quot;mult8_p&quot;  *************</P>
<P CLASS="Computer">
<A NAME="pgfId=264509">
 </A>
    mult8_p</P>
<P CLASS="Computer">
<A NAME="pgfId=264510">
 </A>
        adder8_p</P>
<P CLASS="Computer">
<A NAME="pgfId=264511">
 </A>
         |  full_adder_p [x8]</P>
<P CLASS="Computer">
<A NAME="pgfId=264512">
 </A>
        allzero_p</P>
<P CLASS="Computer">
<A NAME="pgfId=264513">
 </A>
        mux8_p</P>
<P CLASS="Computer">
<A NAME="pgfId=264514">
 </A>
        register8_p</P>
<P CLASS="Computer">
<A NAME="pgfId=264515">
 </A>
         |  dffclr_p [x8]</P>
<P CLASS="Computer">
<A NAME="pgfId=264516">
 </A>
        shiftn_p [x2]</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=264517">
 </A>
        sm_1_p</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=264518">
 </A>
The eight unused instances in question are inside the 8-bit shift register, <SPAN CLASS="BodyComputer">
register8_p</SPAN>
. The only models in this shift register are eight copies of the D flip-flop model, <SPAN CLASS="BodyComputer">
DFFClr</SPAN>
. Let us look more closely at the following code:</P>
<P CLASS="ComputerFirstLabel">
<A NAME="pgfId=264519">
 </A>
<B CLASS="Keyword">
architecture</B>
 Behave <B CLASS="Keyword">
of</B>
 DFFClr <B CLASS="Keyword">
is</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=264520">
 </A>
<B CLASS="Keyword">
signal</B>
 Qi : BIT;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=264521">
 </A>
<B CLASS="Keyword">
begin</B>
<A NAME="20287">
 </A>
 QB &lt;= <B CLASS="Keyword">
not</B>
 Qi; Q &lt;= Qi;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=264522">
 </A>
<B CLASS="Keyword">
process</B>
 (CLR, CLK) <B CLASS="Keyword">
begin</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=264523">
 </A>
	<B CLASS="Keyword">
if</B>
 CLR = '1' <B CLASS="Keyword">
then</B>
 Qi &lt;= '0' <B CLASS="Keyword">
after</B>
 TRQ;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=264524">
 </A>
	<B CLASS="Keyword">
elsif</B>
 CLK'EVENT <B CLASS="Keyword">
and</B>
 CLK = '1' <B CLASS="Keyword">
then</B>
 Qi &lt;= D <B CLASS="Keyword">
after</B>
 TCQ;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=264525">
 </A>
<B CLASS="Keyword">
	end</B>
 <B CLASS="Keyword">
if</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=264526">
 </A>
<B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
process</B>
;</P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=333812">
 </A>
<B CLASS="Keyword">
end</B>
;</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=333816">
 </A>
The synthesizer infers an inverter from the first statement in line <A HREF="#20287" CLASS="XRef">
3</A>
 (<SPAN CLASS="BodyComputer">
QB&nbsp;&lt;=&nbsp;not&nbsp;Qi</SPAN>
). What we meant to imply (A) was: &#8220;I am trying to describe the function of a D flip-flop and it has two outputs; one output is the complement of the other.&#8221; What the synthesizer inferred (B) was: &#8220;You described a D flip-flop with an inverter connected to Q.&#8221; Unfortunately A does not equal B. </P>
<P CLASS="Body">
<A NAME="pgfId=264529">
 </A>
Why were four cell instances (<SPAN CLASS="BodyComputer">
u5</SPAN>
, <SPAN CLASS="BodyComputer">
u2</SPAN>
, <SPAN CLASS="BodyComputer">
u3</SPAN>
, <SPAN CLASS="BodyComputer">
u4</SPAN>
) removed from inside a cell with instance name <SPAN CLASS="BodyComputer">
full_adder_p_dup8</SPAN>
? The top-level cell <SPAN CLASS="BodyComputer">
mult8_p</SPAN>
 contains cell <SPAN CLASS="BodyComputer">
adder8_p</SPAN>
, which in turn contains <SPAN CLASS="BodyComputer">
full_adder_p [x8]</SPAN>
. This last entry in the hierarchy map represents eight occurrences or instances of cell <SPAN CLASS="BodyComputer">
full_adder_p</SPAN>
. The logic synthesizer appends the suffix <SPAN CLASS="BodyComputer">
'_p'</SPAN>
 by default to the names of the design units to avoid overwriting any existing netlists (it also converts all names to lowercase). The synthesizer has then added the suffix <SPAN CLASS="BodyComputer">
'dup8'</SPAN>
 to create the instance name <SPAN CLASS="BodyComputer">
full_adder_p_dup8</SPAN>
 for the eighth copy of cell <SPAN CLASS="BodyComputer">
full_adder_p</SPAN>
.</P>
<P CLASS="Body">
<A NAME="pgfId=265758">
 </A>
What is so special about the eighth instance of <SPAN CLASS="BodyComputer">
full_adder_p</SPAN>
 inside cell <SPAN CLASS="BodyComputer">
adder8_p</SPAN>
? The following (line 13 in Table&nbsp;10.9) instantiates <SPAN CLASS="BodyComputer">
Adder8</SPAN>
:</P>
<P CLASS="ComputerOneLine">
<A NAME="pgfId=265791">
 </A>
A1:Adder8 <B CLASS="Keyword">
port</B>
 <B CLASS="Keyword">
map</B>
(A=&gt;SRB,B=&gt;REGout,Cin=&gt;Low,Cout=&gt;OFL,Sum=&gt;ADDout);</P>
<P CLASS="Body">
<A NAME="pgfId=265662">
 </A>
The signal <SPAN CLASS="BodyComputer">
OFL</SPAN>
 is declared but not used. This means that the formal port name <SPAN CLASS="BodyComputer">
Cout</SPAN>
 for the entity <SPAN CLASS="BodyComputer">
Adder8</SPAN>
 in Table&nbsp;10.2 is unconnected in the instance <SPAN CLASS="BodyComputer">
full_adder_p_dup8</SPAN>
. Since the carry-out bit is unused, the synthesizer deletes some logic. Before dismissing this message as harmless, let us look a little closer. In the architecture for entity <SPAN CLASS="BodyComputer">
Adder8</SPAN>
 we wrote:</P>
<P CLASS="ComputerOneLine">
<A NAME="pgfId=264530">
 </A>
Cout &lt;= (X <B CLASS="Keyword">
and</B>
 Y) <B CLASS="Keyword">
or</B>
 (X <B CLASS="Keyword">
and</B>
 Cin) <B CLASS="Keyword">
or</B>
 (Y <B CLASS="Keyword">
and</B>
 Cin) <B CLASS="Keyword">
after</B>
 TC;</P>
<P CLASS="Body">
<A NAME="pgfId=264531">
 </A>
In one of the instances of <SPAN CLASS="BodyComputer">
Adder8</SPAN>
, named <SPAN CLASS="BodyComputer">
full_adder_p_dup8</SPAN>
, this statement is redundant since we never use <SPAN CLASS="BodyComputer">
Cout</SPAN>
 in that particular cell instance. If we look at the synthesized netlist for <SPAN CLASS="BodyComputer">
full_adder_p_dup8</SPAN>
 before optimization, we find four NAND cells that produce the signal <SPAN CLASS="BodyComputer">
Cout</SPAN>
. During logic optimization the synthesizer removes these four instances. Their instance names are <SPAN CLASS="BodyComputer">
full_adder_p_dup8:u2, u3, u4, u5</SPAN>
.</P>
</DIV>
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