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<TITLE> 12.9 The Multiplier</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
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<H1 CLASS="Heading1">
<A NAME="pgfId=264415">
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12.9 <A NAME="25002">
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The Multiplier</H1>
<P CLASS="BodyAfterHead">
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<A NAME="marker=395388">
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This section looks at the messages that result from attempting to synthesize the VHDL code from Section 10.2, “A 4-bit Multiplier.” The following examples use the line numbers that were assigned in the comments at the end of each line of code in Tables 10.1–10.9. The first problem arises in the following code (line <A HREF="../../../../../../../../Prof.htm#40558" CLASS="XRef">
7</A>
of the full adder in Table 10.1):</P>
<P CLASS="ComputerOneLine">
<A NAME="pgfId=264480">
</A>
Sum <= X xor Y xor Cin after TS;</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=264481">
</A>
<B CLASS="Keyword">
Warning</B>
: AFTER clause in a waveform element is not supported</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=264482">
</A>
This is not a serious problem if you are using a synchronous design style. If you are, then your logic will work whatever the delays (it may run slowly but it will work).</P>
<P CLASS="Body">
<A NAME="pgfId=264929">
</A>
The next problem is from lines <A HREF="../../../../../../../../Prof.htm#33051" CLASS="XRef">
3</A>
–<A HREF="../../../../../../../../Prof.htm#12356" CLASS="XRef">
4</A>
of the 8-bit MUX in Table 10.5,</P>
<P CLASS="ComputerOneLine">
<A NAME="pgfId=264483">
</A>
port (A, B : in BIT_VECTOR (7 downto 0); Sel : in BIT := '0'; Y : out BIT_VECTOR (7 downto 0));</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=264484">
</A>
<B CLASS="Keyword">
Warning</B>
: Default values on interface signals are not supported</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=297139">
</A>
The synthesis tool cannot mimic the behavior of a default value on a port in the software model. The default value is the value given to an input if nothing is connected (<SPAN CLASS="BodyComputer">
'open'</SPAN>
in VHDL). In hardware either an input is connected or it is not. If it is connected, there will be a voltage on the wire. If it is not connected, the node will be floating. Default values are useful in VHDL—without a default value on an input port, an entity–architecture pair will not compile. The default value may be omitted in this model because this input port is connected at the next higher level of hierarchy.</P>
<P CLASS="Body">
<A NAME="pgfId=264977">
</A>
The next problem illustrates what happens when a designer fails to think like the hardware (from line <A HREF="../../../../../../../../Prof.htm#42154" CLASS="XRef">
3</A>
of the zero-detector in Table 10.6),</P>
<P CLASS="ComputerOneLine">
<A NAME="pgfId=264486">
</A>
port (X:BIT_VECTOR; F:out BIT );</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=264487">
</A>
<B CLASS="Keyword">
Error</B>
: An index range must be specified for this data type</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=264488">
</A>
This code has the advantage of being flexible, but the synthesizer needs to know exactly how wide the bus will be. There are two other similar errors in <SPAN CLASS="BodyComputer">
shiftn,</SPAN>
the variable-width shift register (from lines 4–5 in Table 10.7). There are also three more errors generated by the same problem in the component statement for <SPAN CLASS="BodyComputer">
AllZero</SPAN>
(from lines 4–5 of <SPAN CLASS="BodyComputer">
package Mult_Components</SPAN>
) and the component statement for <SPAN CLASS="BodyComputer">
shiftn </SPAN>
(from lines 10–11 of <SPAN CLASS="BodyComputer">
package Mult_Components</SPAN>
).</P>
<P CLASS="Body">
<A NAME="pgfId=265319">
</A>
All of these index range problems may be fixed by sacrificing the flexible nature of the code and specifying an index range explicitly, as in the following example:</P>
<P CLASS="ComputerOneLine">
<A NAME="pgfId=265316">
</A>
port (X:BIT_VECTOR(7 <B CLASS="Keyword">
downto</B>
0); F:out BIT );</P>
<P CLASS="Body">
<A NAME="pgfId=266271">
</A>
<A HREF="#40675" CLASS="XRef">
Table 12.8</A>
shows the synthesizable version of the shift-register model. The constrained index ranges in lines <A HREF="#38616" CLASS="XRef">
6</A>
, <A HREF="#38772" CLASS="XRef">
7</A>
, <A HREF="#10193" CLASS="XRef">
11</A>
, <A HREF="#34641" CLASS="XRef">
18</A>
, <A HREF="#32290" CLASS="XRef">
22</A>
, and <A HREF="#10094" CLASS="XRef">
23</A>
fix the problem, but are rather ugly. It would be better to use <SPAN CLASS="BodyComputer">
generic</SPAN>
parameters for the input and output bus widths. However, a shift register with different input and output widths is not that common so, for now, we will leave the code as it is.</P>
<TABLE>
<TR>
<TH ROWSPAN="1" COLSPAN="2">
<P CLASS="TableTitle">
<A NAME="pgfId=266293">
</A>
TABLE 12.8 <A NAME="40675">
</A>
A synthesizable version of the shift register shown in Table 10.7.</P>
</TH>
</TR>
<TR>
<TD ROWSPAN="2" COLSPAN="1">
<P CLASS="ComputerFirstLabel">
<A NAME="pgfId=266300">
</A>
<B CLASS="Keyword">
entity</B>
ShiftN <B CLASS="Keyword">
is</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=266301">
</A>
<B CLASS="Keyword">
generic </B>
(TCQ:TIME := 0.3 ns; TLQ:TIME := 0.5 ns;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=266302">
</A>
TSQ:TIME := 0.7 ns);</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=266303">
</A>
<B CLASS="Keyword">
port</B>
(</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=266304">
</A>
CLK, CLR, LD, SH, DIR: <B CLASS="Keyword">
in</B>
BIT; </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=266306">
</A>
<A NAME="38616">
</A>
D: <B CLASS="Keyword">
in</B>
BIT_VECTOR(3 <B CLASS="Keyword">
downto</B>
0);</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=266308">
</A>
<A NAME="38772">
</A>
Q: <B CLASS="Keyword">
out</B>
BIT_VECTOR(7 <B CLASS="Keyword">
downto</B>
0) );</P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=266309">
</A>
<B CLASS="Keyword">
end</B>
ShiftN;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=266310">
</A>
<B CLASS="Keyword">
architecture</B>
Behave <B CLASS="Keyword">
of</B>
ShiftN <B CLASS="Keyword">
is</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=266311">
</A>
<B CLASS="Keyword">
begin</B>
Shift: <B CLASS="Keyword">
process</B>
(CLR, CLK)</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=266313">
</A>
<A NAME="10193">
</A>
<B CLASS="Keyword">
variable</B>
St: BIT_VECTOR(7 <B CLASS="Keyword">
downto</B>
0);</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=266314">
</A>
<B CLASS="Keyword">
begin</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=266315">
</A>
<B CLASS="Keyword">
if</B>
CLR = '1' <B CLASS="Keyword">
then</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=266316">
</A>
St := (<B CLASS="Keyword">
others</B>
=> '0'); Q <= St <B CLASS="Keyword">
after</B>
TCQ;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=266317">
</A>
<B CLASS="Keyword">
elsif</B>
CLK'EVENT <B CLASS="Keyword">
and</B>
CLK='1' <B CLASS="Keyword">
then</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=266318">
</A>
<B CLASS="Keyword">
if</B>
LD = '1' <B CLASS="Keyword">
then</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=266319">
</A>
St := (<B CLASS="Keyword">
others</B>
=> '0'); </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=266321">
</A>
<A NAME="34641">
</A>
St(3 <B CLASS="Keyword">
downto</B>
0) := D; </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=266322">
</A>
Q <= St <B CLASS="Keyword">
after</B>
TLQ;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=266323">
</A>
<B CLASS="Keyword">
elsif</B>
SH = '1' <B CLASS="Keyword">
then</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=266324">
</A>
<B CLASS="Keyword">
case</B>
DIR <B CLASS="Keyword">
is</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=266326">
</A>
<A NAME="32290">
</A>
<B CLASS="Keyword">
when</B>
'0'=>St:='0' & St(7 <B CLASS="Keyword">
downto</B>
1);</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=266328">
</A>
<A NAME="10094">
</A>
<B CLASS="Keyword">
when</B>
'1'=>St:=St(6 <B CLASS="Keyword">
downto</B>
0) & '0';</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=266329">
</A>
<B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
case</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=266330">
</A>
Q <= St <B CLASS="Keyword">
after</B>
TSQ;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=266331">
</A>
<B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
if</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=266332">
</A>
<B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
if</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=266333">
</A>
<B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
process</B>
;</P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=266334">
</A>
<B CLASS="Keyword">
end</B>
;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=266339">
</A>
<SUP CLASS="Superscript">
</SUP>
</P>
<DIV>
<IMG SRC="CH12-7.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=266343">
</A>
CLK Clock</P>
<P CLASS="TableLeft">
<A NAME="pgfId=266344">
</A>
CLR Clear, active high</P>
<P CLASS="TableLeft">
<A NAME="pgfId=266345">
</A>
LD Load, active high</P>
<P CLASS="TableLeft">
<A NAME="pgfId=266346">
</A>
SH Shift, active high</P>
<P CLASS="TableLeft">
<A NAME="pgfId=266347">
</A>
DIR Direction, 1=left</P>
<P CLASS="TableLeft">
<A NAME="pgfId=266348">
</A>
D Data in</P>
<P CLASS="TableLeft">
<A NAME="pgfId=266349">
</A>
Q Data out</P>
<P CLASS="TableLeft">
<A NAME="pgfId=266350">
</A>
</P>
<P CLASS="TableLeft">
<A NAME="pgfId=266351">
</A>
Shift register. Input width = 4. Output width = 8. Output is left-shifted or right-shifted under control of DIR. Unused MSBs are zero-padded during load. Clear is asynchronous. Load is synchronous.</P>
<P CLASS="TableLeft">
<A NAME="pgfId=266353">
</A>
</P>
<P CLASS="TableLeft">
<A NAME="pgfId=266354">
</A>
Timing: </P>
<P CLASS="TableLeft">
<A NAME="pgfId=266355">
</A>
<SPAN CLASS="BodyComputer">
TCQ</SPAN>
(CLR to Q) = 0.3 ns</P>
<P CLASS="TableLeft">
<A NAME="pgfId=266356">
</A>
<SPAN CLASS="BodyComputer">
TLQ</SPAN>
(LD to Q) = 0.5 ns</P>
<P CLASS="TableLeft">
<A NAME="pgfId=266357">
</A>
<SPAN CLASS="BodyComputer">
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