ch12.5.htm

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always</B>
@(<B CLASS="Keyword">
posedge</B>
 clock <B CLASS="Keyword">
or</B>
 <B CLASS="Keyword">
negedge</B>
 reset)</P>
<P CLASS="Body">
<A NAME="pgfId=16259">
 </A>
A problem now arises. When we use two edges, the synthesizer must infer which edge is the clock, and which is the reset. Synthesis tools cannot read any significance into the names we have chosen. For example, we could have written</P>
<P CLASS="ComputerOneLine">
<A NAME="pgfId=259635">
 </A>
<B CLASS="Keyword">
always</B>
@(<B CLASS="Keyword">
posedge</B>
 day <B CLASS="Keyword">
or</B>
 <B CLASS="Keyword">
negedge</B>
 year)</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=259633">
 </A>
&#8212;but which is the clock and which is the reset in this case?</P>
<P CLASS="Body">
<A NAME="pgfId=259632">
 </A>
For most synthesis tools you must solve this problem by writing HDL code in a certain format or pattern so that the logic synthesizer may correctly infer the clock and reset signals. The following examples show one possible pattern or <SPAN CLASS="Definition">
template</SPAN>
<A NAME="marker=267911">
 </A>
. These templates and their use are usually described in a <SPAN CLASS="Definition">
synthesis style guide</SPAN>
<A NAME="marker=259673">
 </A>
 that is part of the synthesis software documentation.</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=16247">
 </A>
<B CLASS="Keyword">
always</B>
@(<B CLASS="Keyword">
posedge</B>
 clk <B CLASS="Keyword">
or</B>
 <B CLASS="Keyword">
negedge</B>
 reset) <B CLASS="Keyword">
begin										 									</B>
// template for reset: </P>
<P CLASS="Computer">
<A NAME="pgfId=16249">
 </A>
	<B CLASS="Keyword">
if</B>
 (reset == 0) Q = 0;																		// initialize,</P>
<P CLASS="Computer">
<A NAME="pgfId=16250">
 </A>
	<B CLASS="Keyword">
else</B>
 Q = D;				 														// normal clocking</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=16251">
 </A>
<B CLASS="Keyword">
end</B>
 </P>
<P CLASS="ComputerFirstLabelV">
<A NAME="pgfId=173881">
 </A>
<B CLASS="Keyword">
module</B>
 Counter_With_Reset (count, clock, reset); </P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=173894">
 </A>
<B CLASS="Keyword">
input</B>
 clock, reset; <B CLASS="Keyword">
output</B>
 count; <B CLASS="Keyword">
reg</B>
 [7:0] count;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=70744">
 </A>
<B CLASS="Keyword">
always</B>
 @ (<B CLASS="Keyword">
posedge</B>
 clock <B CLASS="Keyword">
or</B>
 <B CLASS="Keyword">
negedge</B>
 reset) </P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=70745">
 </A>
	<B CLASS="Keyword">
if</B>
 (reset == 0) count = 0; <B CLASS="Keyword">
else</B>
 count = count + 1;</P>
<P CLASS="ComputerLastLabelV">
<A NAME="pgfId=173905">
 </A>
<B CLASS="Keyword">
endmodule</B>
 </P>
<P CLASS="ComputerFirstLabelV">
<A NAME="pgfId=2801">
 </A>
<B CLASS="Keyword">
module</B>
 DFF_MasterSlave (D, clock, reset, Q); // D type flip-flop</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=172565">
 </A>
<B CLASS="Keyword">
input</B>
 D, clock, reset; <B CLASS="Keyword">
output</B>
 Q; <B CLASS="Keyword">
reg</B>
 Q, latch;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=2805">
 </A>
<B CLASS="Keyword">
always</B>
 @(<B CLASS="Keyword">
posedge</B>
 clock <B CLASS="Keyword">
or</B>
 <B CLASS="Keyword">
posedge</B>
 reset)</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=172568">
 </A>
	<B CLASS="Keyword">
if</B>
 (reset == 1) latch = 0; <B CLASS="Keyword">
else</B>
 latch = D; // the master.</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=2809">
 </A>
<B CLASS="Keyword">
always</B>
 @(latch) Q = latch; // the slave.</P>
<P CLASS="ComputerLastLabelV">
<A NAME="pgfId=299917">
 </A>
<B CLASS="Keyword">
endmodule</B>
 </P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=172019">
 </A>
The synthesis tool can now infer that, in these templates, the signal that is tested in the <SPAN CLASS="BodyComputer">
if</SPAN>
 statement is the reset, and that the other signal must therefore be the clock.</P>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=2817">
 </A>
12.5.11&nbsp;Component Instantiation in Verilog</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=70895">
 </A>
When we give an HDL description to a synthesis tool, it will synthesize a netlist that contains generic logic gates. By generic we mean the logic is <A NAME="marker=259682">
 </A>
technology-independent (it could be CMOS standard cell, FPGA, TTL, GaAs, or something else&#8212;we have not decided yet). Only after logic optimization and mapping to a specific ASIC cell library do the speed or area constraints determine the cell choices from a cell library: NAND gates, OAI gates, and so on.  </P>
<P CLASS="Body">
<A NAME="pgfId=223727">
 </A>
The only way to ensure that the synthesizer uses a particular cell, <SPAN CLASS="BodyComputer">
'special'</SPAN>
 for example, from a specific library is to write structural Verilog and instantiate the cell, <SPAN CLASS="BodyComputer">
'special'</SPAN>
, in the Verilog. We call this <SPAN CLASS="Definition">
hand instantiation</SPAN>
<A NAME="marker=259692">
 </A>
. We must then decide whether to allow logic optimization to replace or change <SPAN CLASS="BodyComputer">
'special'</SPAN>
. If we insist on using logic cell <SPAN CLASS="BodyComputer">
'special'</SPAN>
 and do not want it changed, we flag the cell with a synthesizer command. Most logic synthesizers currently use a pseudocomment statement or set an attribute to do this. </P>
<P CLASS="Body">
<A NAME="pgfId=267926">
 </A>
For example, we might include the following statement to tell the Compass synthesizer&#8212;&#8220;Do not change cell instance <SPAN CLASS="BodyComputer">
my_inv_8x</SPAN>
.&#8221; This is not a standard construct, and it is not portable from tool to tool either.</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=173917">
 </A>
//Compass dontTouch my_inv_8x or // synopsys dont_touch</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=173918">
 </A>
INVD8 my_inv_8x(.I(a), .ZN(b) ); </P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=13256">
 </A>
(<SPAN CLASS="BodyComputer">
</SPAN>
<A NAME="marker=395054">
 </A>
some compiler directives are trademarks). Notice, in this example, instantiation involves declaring the instance name and defining a <A NAME="marker=70911">
 </A>
structural port mapping. </P>
<P CLASS="Body">
<A NAME="pgfId=70908">
 </A>
There is no standard name for technology-independent models or components&#8212;we shall call them <SPAN CLASS="Definition">
soft models</SPAN>
<A NAME="marker=70797">
 </A>
 or <SPAN CLASS="Definition">
standard components</SPAN>
<A NAME="marker=260316">
 </A>
. We can use the standard components for synthesis or for behavioral Verilog simulation. Here is an example of using standard components for flip-flops (remember there are no primitive Verilog flip-flop models&#8212;only primitives for the elementary logic cells):</P>
<P CLASS="ComputerFirstLabelV">
<A NAME="pgfId=2843">
 </A>
<B CLASS="Keyword">
module</B>
 Count4(clk, reset, Q0, Q1, Q2, Q3);</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=2845">
 </A>
<B CLASS="Keyword">
input</B>
 clk, reset; <B CLASS="Keyword">
output</B>
 Q0, Q1, Q2, Q3; <B CLASS="Keyword">
wire</B>
 Q0, Q1, Q2, Q3;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=2855">
 </A>
// &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Q ,  D , clk, reset</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=2857">
 </A>
asDff dff0( Q0,  ~Q0, clk, reset); // The asDff is a</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=2859">
 </A>
asDff dff1( Q1,  ~Q1, Q0,  reset); // standard component,</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=2861">
 </A>
asDff dff2( Q2,  ~Q2, Q1,  reset); // unique to one set of tools.</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=2863">
 </A>
asDff dff3( Q3,  ~Q3, Q2,  reset);</P>
<P CLASS="ComputerLastLabelV">
<A NAME="pgfId=2873">
 </A>
<B CLASS="Keyword">
endmodule</B>
 </P>
<P CLASS="Body">
<A NAME="pgfId=396289">
 </A>
The <SPAN CLASS="BodyComputer">
asDff </SPAN>
and other standard components are provided with the synthesis tool. The standard components have specific names and interfaces that are part of the software documentation. When we use a standard component such as <SPAN CLASS="BodyComputer">
asDff </SPAN>
we are saying: &#8220;I want a D flip-flop, but I do not know which ASIC technology I want to use&#8212;give me a generic version. I do not want to write a Verilog model for the D flip-flop myself because I do not want to bother to synthesize each and every instance of a flip-flop. When the time comes, just map this generic flip-flop to whatever is available in the technology-dependent (vendor-specific) library.&#8221; </P>
<P CLASS="Body">
<A NAME="pgfId=260645">
 </A>
If we try and simulate <SPAN CLASS="BodyComputer">
Count4</SPAN>
 we will get an error,</P>
<P CLASS="ComputerOneLine">
<A NAME="pgfId=260646">
 </A>
:Count4.v: L5: error: Module 'asDff' not defined</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=260647">
 </A>
(and three more like this) because <SPAN CLASS="BodyComputer">
asDff</SPAN>
 is not a primitive Verilog model. The synthesis tool should provide us with a model for the standard component. For example, the following code models the behavior of the standard component, <SPAN CLASS="BodyComputer">
asDff</SPAN>
:</P>
<P CLASS="ComputerFirstLabelV">
<A NAME="pgfId=260654">
 </A>
<B CLASS="Keyword">
module</B>
 asDff (D, Q, Clk, Rst); </P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=292684">
 </A>
<B CLASS="Keyword">
parameter</B>
 width = 1, reset_value = 0;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=260656">
 </A>
<B CLASS="Keyword">
input</B>
 [width-1:0] D; <B CLASS="Keyword">
output</B>
 [width-1:0] Q; reg [width-1:0] Q;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=260659">
 </A>
<B CLASS="Keyword">
input</B>
 Clk,Rst; <B CLASS="Keyword">
initial</B>
 Q = {width{1'bx}};</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=260663">
 </A>
	<B CLASS="Keyword">
always</B>
 @ ( <B CLASS="Keyword">
posedge</B>
 Clk <B CLASS="Keyword">
or</B>
 <B CLASS="Keyword">
negedge</B>
 Rst )</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=260664">
 </A>
		<B CLASS="Keyword">
if</B>
 ( Rst==0 ) Q &lt;= #1 reset_value; <B CLASS="Keyword">
else</B>
 Q &lt;= #1 D;</P>
<P CLASS="ComputerLastLabelV">
<A NAME="pgfId=260666">
 </A>
<B CLASS="Keyword">
endmodule</B>
 </P>
<P CLASS="Body">
<A NAME="pgfId=260650">
 </A>
When the synthesizer compiles the HDL code in <SPAN CLASS="BodyComputer">
Count4</SPAN>
, it does not parse the <SPAN CLASS="BodyComputer">
asDff</SPAN>
 model. The software recognizes <SPAN CLASS="BodyComputer">
asDff</SPAN>
 and says &#8220;I see you want a flip-flop.&#8221; The first steps that the synthesis software and the simulation software take are often referred to as compilation, but the two steps are different for each of these tools.</P>
<P CLASS="Body">
<A NAME="pgfId=260730">
 </A>
Synopsys has an extensive set of libraries, called <SPAN CLASS="Definition">
DesignWare</SPAN>
<A NAME="marker=259749">
 </A>
, that contains standard components not only for flip-flops but for arithmetic and other complex logic elements. These standard components are kept protected from optimization until it is time to map to a vendor technology. ASIC or EDA companies that produce design software and cell libraries can tune the synthesizer to the silicon and achieve a more efficient mapping. Even though we call them standard components, there are no standards that cover their names, use, interfaces, or models. </P>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=16460">
 </A>
12.5.12&nbsp;<A NAME="25859">
 </A>
Datapath Synthesis in Verilog</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=2893">
 </A>
<A NAME="marker=395340">
 </A>
Datapath synthesis is used for bus-wide arithmetic and other bus-wide operations. For example, synthesis of a 32-bit multiplier in random logic is much less efficient than using datapath synthesis. There are several approaches to datapath synthesis:</P>
<UL>
<LI CLASS="BulletFirst">
<A NAME="pgfId=259889">
 </A>
Synopsys VHDL DesignWare. This models generic arithmetic and other large functions (counters, shift registers, and so on) using standard components. We can either let the synthesis tool map operators (such as <SPAN CLASS="BodyComputer">
'+'</SPAN>
) to VHDL DesignWare components, or we can hand instantiate them in the code. Many ASIC vendors support the DesignWare libraries. Thus, for example, we can instantiate a DesignWare counter in VHDL and map that to a cell predesigned and preoptimized by Actel for an Actel FPGA.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=259923">
 </A>
<A NAME="marker=395339">
 </A>
Compiler directives. This approach uses <A NAME="marker=395338">
 </A>
synthesis directives in the code to steer the mapping of datapath operators either to specific components (a two-port RAM or a register file, for example) or flags certain operators to be implemented using a certain style (<SPAN CLASS="BodyComputer">
'+'</SPAN>
 to be implemented using a ripple-carry adder or a carry-lookahead adder, for example). </LI>
<LI CLASS="BulletList">
<A NAME="pgfId=267951">
 </A>
<A NAME="marker=395333">
 </A>
X-BLOX is a system from Xilinx that allows us to keep the logic of certain functions (counters, arithmetic elements) together. This is so that the layout tool does not splatter the synthesized CLBs all over your FPGA, reducing the performance of the logic.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=267952">
 </A>
<A NAME="marker=395334">
 </A>
LPM (<A NAME="marker=395336">
 </A>
library of parameterized modules) and <A NAME="marker=395335">
 </A>
RPM (<A NAME="marker=395337">
 </A>
relationally placed modules) are other techniques used principally by FPGA companies to keep logic that operates on related data close together. This approach is based on the use of the EDIF language to describe the modules.</LI>
</UL>
<P CLASS="Body">
<A NAME="pgfId=267963">
 </A>
In all cases the disadvantage is that the code becomes specific to a certain piece of software. Here are two examples of datapath synthesis directives:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=259924">
 </A>
<B CLASS="Keyword">
module</B>
 DP_csum(A1,B1,Z1); <B CLASS="Keyword">
input</B>
 [3:0] A1,B1; <B CLASS="Keyword">
output</B>
 Z1; <B CLASS="Keyword">
reg</B>
 [3:0] Z1;</P>
<P CLASS="Computer">
<A NAME="pgfId=259914">
 </A>
<B CLASS="Keyword">
always</B>
@(A1 <B CLASS="Keyword">
or</B>
 B1) Z1 &lt;= A1 + B1;//Compass adder_arch cond_sum_add</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=259916">
 </A>
<B CLASS="Keyword">
endmodule</B>
 </P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=259953">
 </A>
<B CLASS