ch12.5.htm

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wire</SPAN>
 rather than a <SPAN CLASS="BodyComputer">
reg</SPAN>
),</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=174145">
 </A>
<B CLASS="Keyword">
module</B>
 And_Assign(x, y, z); <B CLASS="Keyword">
input</B>
 x,y; <B CLASS="Keyword">
output</B>
 z; <B CLASS="Keyword">
wire</B>
 z;</P>
<P CLASS="Computer">
<A NAME="pgfId=174154">
 </A>
<B CLASS="Keyword">
assign</B>
 z &lt;= x &amp; y; // combinational logic method 2 = method 1</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=174149">
 </A>
<B CLASS="Keyword">
endmodule</B>
 </P>
<P CLASS="Body">
<A NAME="pgfId=12316">
 </A>
We may also use concatenation or bit reduction to synthesize combinational logic functions, </P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=12317">
 </A>
<B CLASS="Keyword">
module</B>
 And_Or (a,b,c,z); <B CLASS="Keyword">
input</B>
 a,b,c; <B CLASS="Keyword">
output</B>
 z; <B CLASS="Keyword">
reg</B>
 [1:0]z; </P>
<P CLASS="Computer">
<A NAME="pgfId=174182">
 </A>
<B CLASS="Keyword">
always</B>
 @(a <B CLASS="Keyword">
or</B>
 b <B CLASS="Keyword">
or</B>
 c) <B CLASS="Keyword">
begin</B>
 z[1]&lt;= &amp;{a,b,c}; z[2]&lt;= |{a,b,c}; <B CLASS="Keyword">
end</B>
</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=187894">
 </A>
<B CLASS="Keyword">
endmodule</B>
 </P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=187896">
 </A>
<B CLASS="Keyword">
module</B>
 Parity (BusIn, outp); <B CLASS="Keyword">
input</B>
[7:0] BusIn; <B CLASS="Keyword">
output</B>
 outp; <B CLASS="Keyword">
reg</B>
 outp;</P>
<P CLASS="Computer">
<A NAME="pgfId=174289">
 </A>
	<B CLASS="Keyword">
always</B>
 @(BusIn) <B CLASS="Keyword">
if</B>
 (^Busin == 0) outp = 1; <B CLASS="Keyword">
else</B>
 outp = 0;</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=12501">
 </A>
<B CLASS="Keyword">
endmodule</B>
 </P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=12288">
 </A>
The number of inputs, the types, and the drive strengths of the synthesized combinational logic cells will depend on the speed, area, and load requirements that you set as constraints. </P>
<P CLASS="Body">
<A NAME="pgfId=173812">
 </A>
You must be careful if you reference a signal (<SPAN CLASS="BodyComputer">
reg</SPAN>
 or <SPAN CLASS="BodyComputer">
wire</SPAN>
) in a level-sensitive <SPAN CLASS="BodyComputer">
always</SPAN>
 statement and do not include that signal in the sensitivity list. In the following example, signal <SPAN CLASS="BodyComputer">
b</SPAN>
 is missing from the sensitivity list, and so this code should be flagged with a warning or an error by the synthesis tool&#8212;even though the code is perfectly legal and acceptable to the Verilog simulator:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=174109">
 </A>
<B CLASS="Keyword">
module</B>
 And_Bad(a, b, c); <B CLASS="Keyword">
input</B>
 a, b; <B CLASS="Keyword">
output</B>
 c; <B CLASS="Keyword">
reg</B>
 c;</P>
<P CLASS="Computer">
<A NAME="pgfId=174110">
 </A>
<B CLASS="Keyword">
always</B>
@(a) c &lt;= a &amp; b; // b is missing from this sensitivity list</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=174111">
 </A>
<B CLASS="Keyword">
endmodule</B>
 </P>
<P CLASS="Body">
<A NAME="pgfId=174112">
 </A>
It is easy to write Verilog code that will simulate, but that does not make sense to the synthesis software. You must think like the hardware. To avoid this type of problem with combinational logic inside an <SPAN CLASS="BodyComputer">
always</SPAN>
 statement you should either:</P>
<UL>
<LI CLASS="BulletFirst">
<A NAME="pgfId=257913">
 </A>
include all variables in the event expression or</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=257914">
 </A>
assign to the variables before you use them</LI>
</UL>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=257915">
 </A>
For example, consider the following two models:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=257841">
 </A>
<B CLASS="Keyword">
module</B>
 CL_good(a, b, c); <B CLASS="Keyword">
input</B>
 a, b; <B CLASS="Keyword">
output</B>
 c; <B CLASS="Keyword">
reg</B>
 c;</P>
<P CLASS="Computer">
<A NAME="pgfId=257842">
 </A>
<B CLASS="Keyword">
always</B>
@(a or b)</P>
<P CLASS="Computer">
<A NAME="pgfId=257850">
 </A>
<B CLASS="Keyword">
begin</B>
 c = a + b; d = a &amp; b; e = c + d; <B CLASS="Keyword">
end</B>
 // c, d: LHS before RHS</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=257843">
 </A>
<B CLASS="Keyword">
endmodule</B>
 </P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=257871">
 </A>
<B CLASS="Keyword">
module</B>
 CL_bad(a, b, c); <B CLASS="Keyword">
input</B>
 a, b; <B CLASS="Keyword">
output</B>
 c; <B CLASS="Keyword">
reg</B>
 c;</P>
<P CLASS="Computer">
<A NAME="pgfId=257872">
 </A>
<B CLASS="Keyword">
always</B>
@(a or b)</P>
<P CLASS="Computer">
<A NAME="pgfId=257873">
 </A>
<B CLASS="Keyword">
begin</B>
 e = c + d; c = a + b; d = a &amp; b; <B CLASS="Keyword">
end</B>
 // c, d: RHS before LHS</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=257877">
 </A>
<B CLASS="Keyword">
endmodule</B>
 </P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=257839">
 </A>
In <SPAN CLASS="BodyComputer">
CL_bad</SPAN>
, the signals <SPAN CLASS="BodyComputer">
c</SPAN>
 and <SPAN CLASS="BodyComputer">
d</SPAN>
 are used on the right-hand side (RHS) of an assignment statement before they are defined on the left-hand side (LHS) of an assignment statement. If the logic synthesizer produces combinational logic for <SPAN CLASS="BodyComputer">
CL_bad</SPAN>
, it should warn us that the synthesized logic may not match the simulation results.</P>
<P CLASS="Body">
<A NAME="pgfId=245790">
 </A>
When you are describing combinational logic you should be aware of the complexity of logic optimization. Some combinational logic functions are too difficult for the optimization algorithms to handle. The following module, <SPAN CLASS="BodyComputer">
Achilles</SPAN>
, and large parity functions are examples of hard-to-synthesize functions. This is because most logic-optimization algorithms calculate the complement of the functions at some point. The complements of certain functions grow exponentially in the number of their product terms.</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=245793">
 </A>
// The complement of this function is too big for synthesis.</P>
<P CLASS="Computer">
<A NAME="pgfId=245795">
 </A>
<B CLASS="Keyword">
module</B>
 Achilles (out, in); <B CLASS="Keyword">
output</B>
 out; <B CLASS="Keyword">
input</B>
 [30:1] in;</P>
<P CLASS="Computer">
<A NAME="pgfId=245799">
 </A>
<B CLASS="Keyword">
assign</B>
 out = 						&nbsp;&nbsp;in[30]&amp;in[29]&amp;in[28] | in[27]&amp;in[26]&amp;in[25]</P>
<P CLASS="Computer">
<A NAME="pgfId=245800">
 </A>
						| in[24]&amp;in[23]&amp;in[22] | in[21]&amp;in[20]&amp;in[19]</P>
<P CLASS="Computer">
<A NAME="pgfId=245801">
 </A>
						| in[18]&amp;in[17]&amp;in[16] | in[15]&amp;in[14]&amp;in[13]</P>
<P CLASS="Computer">
<A NAME="pgfId=245802">
 </A>
						| in[12]&amp;in[11]&amp;in[10] | in[9]&nbsp;&amp; in[8]&amp;in[7]</P>
<P CLASS="Computer">
<A NAME="pgfId=245803">
 </A>
						| in[6]&nbsp;&amp; in[5]&amp;in[4]  | in[3]&nbsp;&amp; in[2]&amp;in[1];</P>
<P CLASS="Computer">
<A NAME="pgfId=245804">
 </A>
<B CLASS="Keyword">
endmodule</B>
 </P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=326063">
 </A>
In a case like this you can isolate the problem function in a separate module. Then, after synthesis, you can use directives to tell the synthesizer not to try and optimize the problem function. </P>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=173230">
 </A>
12.5.5&nbsp;Multiplexers In Verilog</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=173231">
 </A>
We imply a MUX using a <SPAN CLASS="BodyComputer">
case</SPAN>
 statement, as in the following example:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=257982">
 </A>
<B CLASS="Keyword">
module</B>
 Mux_21a(sel, a, b, z); <B CLASS="Keyword">
input</B>
 sel, a , b; <B CLASS="Keyword">
output</B>
 z; <B CLASS="Keyword">
reg</B>
 z;</P>
<P CLASS="Computer">
<A NAME="pgfId=257985">
 </A>
<B CLASS="Keyword">
always</B>
 @(a <B CLASS="Keyword">
or</B>
 b <B CLASS="Keyword">
or</B>
 sel)</P>
<P CLASS="Computer">
<A NAME="pgfId=257986">
 </A>
<B CLASS="Keyword">
begin case</B>
(sel) 1'b0: z &lt;= a; 1'b1: z &lt;= b; <B CLASS="Keyword">
end</B>
</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=257987">
 </A>
<B CLASS="Keyword">
endmodule</B>
 </P>
<P CLASS="Body">
<A NAME="pgfId=257978">
 </A>
Be careful using <SPAN CLASS="BodyComputer">
'x'</SPAN>
 in a <SPAN CLASS="BodyComputer">
case</SPAN>
 statement. <A NAME="marker=340737">
 </A>
Metalogical values (such as <SPAN CLASS="BodyComputer">
'x'</SPAN>
) are not &#8220;real&#8221; and are only valid in simulation (and they are sometimes known as <SPAN CLASS="Definition">
simbits</SPAN>
<A NAME="marker=258058">
 </A>
 for that reason). For example, a synthesizer cannot make logic to model the following and will usually issue a warning to that effect:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=258026">
 </A>
<B CLASS="Keyword">
module</B>
 Mux_x(sel, a, b, z); <B CLASS="Keyword">
input</B>
 sel, a, b; <B CLASS="Keyword">
output</B>
 z; <B CLASS="Keyword">
reg</B>
 z;</P>
<P CLASS="Computer">
<A NAME="pgfId=258028">
 </A>
<B CLASS="Keyword">
always</B>
 @(a <B CLASS="Keyword">
or</B>
 b <B CLASS="Keyword">
or</B>
 sel)</P>
<P CLASS="Computer">
<A NAME="pgfId=258029">
 </A>
<B CLASS="Keyword">
begin case</B>
(sel) 1'b0: z &lt;= 0; 1'b1: z &lt;= 1; 1'bx: z &lt;= 'x'; <B CLASS="Keyword">
end</B>
</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=258030">
 </A>
<B CLASS="Keyword">
endmodule</B>
 </P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=257979">
 </A>
For the same reason you should avoid using <SPAN CLASS="BodyComputer">
casex</SPAN>
 and <SPAN CLASS="BodyComputer">
casez</SPAN>
 statements.</P>
<P CLASS="Body">
<A NAME="pgfId=258074">
 </A>
An <SPAN CLASS="BodyComputer">
if </SPAN>
statement can also be used to imply a MUX as follows:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=258077">
 </A>
<B CLASS="Keyword">
module</B>
 Mux_21b(sel, a, b, z); <B CLASS="Keyword">
input</B>
 sel, a, b; <B CLASS="Keyword">
output</B>
 z; <B CLASS="Keyword">
reg</B>
 z;</P>
<P CLASS="Computer">
<A NAME="pgfId=258078">
 </A>
<B CLASS="Keyword">
always</B>
 @(a <B CLASS="Keyword">
or</B>
 b <B CLASS="Keyword">
or</B>
 sel) <B CLASS="Keyword">
begin if </B>
(sel) z &lt;= a <B CLASS="Keyword">
else </B>
z &lt;= b; <B CLASS="Keyword">
end</B>
</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=258080">
 </A>
<B CLASS="Keyword">
endmodule</B>
 </P>
<P CLASS="Body">
<A NAME="pgfId=258075">
 </A>
However, if you do not always assign to an output, as in the following code, you will get a latch:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=258187">
 </A>
<B CLASS="Keyword">
module</B>
 Mux_Latch(sel, a, b, z); <B CLASS="Keyword">
input</B>
 sel, a, b; <B CLASS="Keyword">
output</B>
 z; <B CLASS="Keyword">
reg</B>
 z;</P>
<P CLASS="Computer">
<A NAME="pgfId=258212">
 </A>
<B CLASS="Keyword">
always</B>
 @(a <B CLASS="Keyword">
or</B>
 sel) <B CLASS="Keyword">
begin if </B>
(sel) z &lt;= a; <B CLASS="Keyword">
end</B>
</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=258190">