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<TITLE> 12.5 Verilog and Logic Synthesis</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
<DIV>
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<H1 CLASS="Heading1">
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12.5 <A NAME="18222">
</A>
Verilog and Logic Synthesis</H1>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=284337">
</A>
A top-down design approach using Verilog begins with a single <SPAN CLASS="BodyComputer">
module</SPAN>
at the top of the hierarchy to model the input and output response of the ASIC:</P>
<P CLASS="ComputerOneLine">
<A NAME="pgfId=284338">
</A>
<B CLASS="Keyword">
module</B>
MyChip_ASIC(); ... (code to model ASIC I/O) ... <B CLASS="Keyword">
endmodule</B>
;</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=284339">
</A>
This top-level Verilog module is used to simulate the ASIC I/O connections and any bus I/O during the earliest stages of design. Often the reason that designs fail is lack of attention to the connection between the ASIC and the rest of the system.</P>
<P CLASS="Body">
<A NAME="pgfId=284340">
</A>
As a designer, you proceed down through the hierarchy as you add lower-level modules to the top-level Verilog module. Initially the lower-level modules are just empty placeholders, or <A NAME="marker=284341">
</A>
<SPAN CLASS="Definition">
stubs</SPAN>
, containing a minimum of code. For example, you might start by using inverters just to connect inputs directly to the outputs. You expand these stubs before moving down to the next level of modules.</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=284342">
</A>
<B CLASS="Keyword">
module</B>
MyChip_ASIC()</P>
<P CLASS="Computer">
<A NAME="pgfId=284343">
</A>
// behavioral "always", etc. ...</P>
<P CLASS="Computer">
<A NAME="pgfId=284344">
</A>
SecondLevelStub1 port mapping</P>
<P CLASS="Computer">
<A NAME="pgfId=284345">
</A>
SecondLevelStub2 port mapping</P>
<P CLASS="Computer">
<A NAME="pgfId=284346">
</A>
... <B CLASS="Keyword">
endmodule</B>
</P>
<P CLASS="Computer">
<A NAME="pgfId=284347">
</A>
<B CLASS="Keyword">
module</B>
SecondLevelStub1() ... <B CLASS="Keyword">
assign</B>
Output1 = ~Input1; <B CLASS="Keyword">
endmodule</B>
</P>
<P CLASS="Computer">
<A NAME="pgfId=284348">
</A>
<B CLASS="Keyword">
module</B>
SecondLevelStub2() ... <B CLASS="Keyword">
assign</B>
Output2 = ~Input2;</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=284349">
</A>
<B CLASS="Keyword">
endmodule</B>
</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=284350">
</A>
Eventually the Verilog modules will correspond to the various component pieces of the ASIC. </P>
<DIV>
<H2 CLASS="Heading2">
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</A>
12.5.1 Verilog Modeling</H2>
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<A NAME="pgfId=7037">
</A>
Before we could start synthesis of the Viterbi decoder we had to alter the model for the D flip-flop. This was because the original flip-flop model contained syntax (multiple <SPAN CLASS="BodyComputer">
wait</SPAN>
statements in an <SPAN CLASS="BodyComputer">
always</SPAN>
statement) that was acceptable to the simulation tool but not by the synthesis tool. This example was artificial because we had already prepared and tested the Verilog code so that it was acceptable to the synthesis software (we say we created <SPAN CLASS="Definition">
synthesizable</SPAN>
<A NAME="marker=263961">
</A>
code). However, finding ourselves with nonsynthesizable code arises frequently in logic synthesis. The original OVI LRM included a <A NAME="marker=2247">
</A>
<SPAN CLASS="Definition">
synthesis policy</SPAN>
, a set of guidelines that outline which parts of the Verilog language a synthesis tool should support and which parts are optional. Some EDA vendors call their synthesis policy a <A NAME="marker=284791">
</A>
<SPAN CLASS="Definition">
modeling style</SPAN>
. There is no current standard on which parts of an HDL (either Verilog or VHDL) a synthesis tool should support.</P>
<P CLASS="Body">
<A NAME="pgfId=284784">
</A>
It is essential that the structural model created by a synthesis tool is <A NAME="marker=2269">
</A>
<SPAN CLASS="Definition">
functionally identical</SPAN>
, or <A NAME="marker=2272">
</A>
<SPAN CLASS="Definition">
functionally equivalent</SPAN>
, to your behavioral model. Hopefully, we know this is true if the synthesis tool is working properly. In this case the logic is “correct by construction.” If you use different HDL code for simulation and for synthesis, you have a problem. The process of <SPAN CLASS="Emphasis">
formal verification</SPAN>
can prove that two logic descriptions (perhaps structural and behavioral HDL descriptions) are identical in their behavior. We shall return to this issue in Chapter 13.</P>
<P CLASS="Body">
<A NAME="pgfId=263954">
</A>
Next we shall examine Verilog and VHDL from the following viewpoint: “How do I write synthesizable code?”</P>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=2281">
</A>
12.5.2 <A NAME="26422">
</A>
Delays in Verilog</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=15618">
</A>
Synthesis tools ignore delay values. They must—how can a synthesis tool guarantee that logic will have a certain delay? For example, a synthesizer cannot generate hardware to implement the following Verilog code:</P>
<P CLASS="ComputerFirstLabelV">
<A NAME="pgfId=2283">
</A>
<B CLASS="Keyword">
module</B>
Step_Time(clk, phase);</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=2285">
</A>
<B CLASS="Keyword">
input</B>
clk; <B CLASS="Keyword">
output</B>
[2:0] phase; <B CLASS="Keyword">
reg</B>
[2:0] phase;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=2287">
</A>
<B CLASS="Keyword">
always</B>
@(<B CLASS="Keyword">
posedge</B>
clk) <B CLASS="Keyword">
begin</B>
</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=2291">
</A>
phase <= 4'b0000; </P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=223228">
</A>
phase <= #1 4'b0001; phase <= #2 4'b0010;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=2297">
</A>
phase <= #3 4'b0011; phase <= #4 4'b0100;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=2301">
</A>
<B CLASS="Keyword">
end</B>
</P>
<P CLASS="ComputerLastLabelV">
<A NAME="pgfId=2303">
</A>
<B CLASS="Keyword">
endmodule</B>
</P>
<P CLASS="Body">
<A NAME="pgfId=17296">
</A>
We can avoid this type of timing problem by dividing a clock as follows:</P>
<P CLASS="ComputerFirstLabelV">
<A NAME="pgfId=2309">
</A>
<B CLASS="Keyword">
module</B>
Step_Count (clk_5x, phase);</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=2311">
</A>
<B CLASS="Keyword">
input</B>
clk_5x; <B CLASS="Keyword">
output</B>
[2:0] phase; <B CLASS="Keyword">
reg</B>
[2:0] phase;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=2313">
</A>
<B CLASS="Keyword">
always</B>
@(<B CLASS="Keyword">
posedge</B>
clk_5x)</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=2315">
</A>
<B CLASS="Keyword">
case</B>
(phase)</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=2317">
</A>
0:phase = #1 1; 1:phase = #1 2; 2:phase = #1 3; 3:phase = #1 4;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=2325">
</A>
<B CLASS="Keyword">
default</B>
: phase = #1 0;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=2327">
</A>
<B CLASS="Keyword">
endcase</B>
</P>
<P CLASS="ComputerLastLabelV">
<A NAME="pgfId=257577">
</A>
<B CLASS="Keyword">
endmodule</B>
</P>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=257641">
</A>
12.5.3 <A NAME="38330">
</A>
Blocking and Nonblocking Assignments</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=70343">
</A>
There are some synthesis limitations that arise from the different types of Verilog assignment statements. Consider the following shift-register model:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=70344">
</A>
<B CLASS="Keyword">
module</B>
race(clk, q0); <B CLASS="Keyword">
input</B>
clk, q0; <B CLASS="Keyword">
reg</B>
q1, q2;</P>
<P CLASS="Computer">
<A NAME="pgfId=70347">
</A>
<B CLASS="Keyword">
always</B>
@(<B CLASS="Keyword">
posedge</B>
clk) q1 = #1 q0; <B CLASS="Keyword">
always</B>
@(<B CLASS="Keyword">
posedge</B>
clk) q2 = #1 q1;</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=70349">
</A>
<B CLASS="Keyword">
endmodule</B>
</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=15692">
</A>
This example has a <SPAN CLASS="Definition">
race condition</SPAN>
<A NAME="marker=392678">
</A>
(or a <SPAN CLASS="Definition">
race</SPAN>
<A NAME="marker=392679">
</A>
) that occurs as follows. The synthesizer ignores delays and the two <SPAN CLASS="BodyComputer">
always</SPAN>
statements are procedures that execute concurrently. So, do we update <SPAN CLASS="BodyComputer">
q1</SPAN>
first and then assign the new value of <SPAN CLASS="BodyComputer">
q1</SPAN>
to <SPAN CLASS="BodyComputer">
q2</SPAN>
? or do we update <SPAN CLASS="BodyComputer">
q2</SPAN>
first (with the old value of <SPAN CLASS="BodyComputer">
q1</SPAN>
), and then update <SPAN CLASS="BodyComputer">
q1</SPAN>
? In real hardware two signals would be racing each other—and the winner is unclear. We must think like the hardware to guide the synthesis tool. Combining the assignment statements into a single <SPAN CLASS="BodyComputer">
always</SPAN>
statement, as follows, is one way to solve this problem:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=18095">
</A>
<B CLASS="Keyword">
module</B>
no_race_1(clk, q0, q2); <B CLASS="Keyword">
input</B>
clk, q0; <B CLASS="Keyword">
output</B>
q2; <B CLASS="Keyword">
reg</B>
q1, q2;</P>
<P CLASS="Computer">
<A NAME="pgfId=15695">
</A>
<B CLASS="Keyword">
always</B>
@(<B CLASS="Keyword">
posedge</B>
clk) <B CLASS="Keyword">
begin </B>
q2 = q1; q1 = q0; <B CLASS="Keyword">
end</B>
</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=18091">
</A>
<B CLASS="Keyword">
endmodule</B>
</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=98542">
</A>
Evaluation is sequential within an <SPAN CLASS="BodyComputer">
always</SPAN>
statement, and the order of the assignment statements now ensures <SPAN CLASS="BodyComputer">
q2</SPAN>
gets the old value of <SPAN CLASS="BodyComputer">
q1</SPAN>
—before we update <SPAN CLASS="BodyComputer">
q1</SPAN>
.</P>
<P CLASS="Body">
<A NAME="pgfId=15701">
</A>
We can also avoid the problem if we use nonblocking assignment statements,</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=18174">
</A>
<B CLASS="Keyword">
module</B>
no_race_2(clk, q0, q2); <B CLASS="Keyword">
input</B>
clk, q0; <B CLASS="Keyword">
output</B>
q2; <B CLASS="Keyword">
reg</B>
q1, q2;</P>
<P CLASS="Computer">
<A NAME="pgfId=15704">
</A>
<B CLASS="Keyword">
always</B>
@(<B CLASS="Keyword">
posedge</B>
clk) q1 <= #1 q0; <B CLASS="Keyword">
always</B>
@(<B CLASS="Keyword">
posedge</B>
clk) q2 <= #1 q1;</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=18181">
</A>
<B CLASS="Keyword">
endmodule</B>
</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=98534">
</A>
This code updates all the registers together, at the end of a time step, so <SPAN CLASS="BodyComputer">
q2</SPAN>
always gets the old value of <SPAN CLASS="BodyComputer">
q1</SPAN>
.</P>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=18161">
</A>
12.5.4 <A NAME="35152">
</A>
Combinational Logic in Verilog</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=18145">
</A>
To model combinational logic, the sensitivity list of a Verilog always statement must contain only signals with no edges (no reference to keywords <SPAN CLASS="BodyComputer">
posedge</SPAN>
or <SPAN CLASS="BodyComputer">
negedge</SPAN>
). This is a <SPAN CLASS="Definition">
level-sensitive</SPAN>
<A NAME="marker=259369">
</A>
sensitivity list—as in the following example that implies a two-input AND gate:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=16414">
</A>
<B CLASS="Keyword">
module</B>
And_Always(x, y, z); <B CLASS="Keyword">
input</B>
x,y; <B CLASS="Keyword">
output</B>
z; <B CLASS="Keyword">
reg</B>
z; </P>
<P CLASS="Computer">
<A NAME="pgfId=174134">
</A>
<B CLASS="Keyword">
always</B>
@(x <B CLASS="Keyword">
or</B>
y) z <= x & y; // combinational logic method 1 </P>
<P CLASS="ComputerLast">
<A NAME="pgfId=174141">
</A>
<B CLASS="Keyword">
endmodule</B>
</P>
<P CLASS="Body">
<A NAME="pgfId=16417">
</A>
Continuous assignment statements also imply combinational logic (notice that <SPAN CLASS="BodyComputer">
z</SPAN>
is now a <SPAN CLASS="BodyComputer">
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