ch12.c.htm

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&nbsp;</P>
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&nbsp;</P>
<P CLASS="Computer">
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u5.sub_rip1.u6</P>
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u5.sub_rip1.u8</P>
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B1_i301</P>
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u2.metric3.Q_ff_b4</P>
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&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Computer">
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inPin --&gt; outPin       incr    arrival trs  rampDel  cap(pF) cell </P>
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&nbsp;</P>
<P CLASS="Computer">
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CP --&gt; QN              1.65     1.65    F    .20     .10    dfctnb</P>
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A1 --&gt; ZN               .63     2.27    R    .14     .08    ao01d1</P>
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B --&gt; ZN                .84     3.12    F    .15     .08    ao04d1</P>
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B2 --&gt; ZN               .91     4.03    F    .35     .17    fn03d1</P>
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I --&gt; ZN                .39     4.43    R    .23     .12    in01d1</P>
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S --&gt; Z                 .91     5.33    F    .34     .17    mx21d1</P>
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B0 --&gt; CO              2.20     7.54    F    .24     .14    ad02d1</P>
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&nbsp;</P>
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... 28 other cell instances omitted ...</P>
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&nbsp;</P>
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B0 --&gt; CO              2.25    23.17    F    .23     .13    ad02d1</P>
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CI --&gt; CO               .53    23.70    F    .21     .09    ad01d1</P>
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<A NAME="pgfId=394024">
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A1 --&gt; Z                .69    24.39    R    .19     .07    xo02d1</P>
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setup: D --&gt; CP         .17    24.56    R    .00     .00    dfctnb</P>
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slack: MET                       .44 </P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
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<A HREF="#26932" CLASS="XRef">
Table&nbsp;12.13</A>
 is a timing report for the Viterbi decoder, which shows the critical path starts at a sequential logic cell (a D flip-flop in the present example), ends at a sequential logic cell (another D flip-flop), with 37 other combinational logic cells in-between. The first delay is the clock-to-Q delay of the first flip-flop. The last delay is the setup time of the last flip-flop. The critical path delay is 24.56  ns, which gives a <SPAN CLASS="Definition">
slack</SPAN>
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 of 0.44  ns from the constraint of 25  ns (reduced from 30  ns to give an extra margin). We have <SPAN CLASS="Definition">
met</SPAN>
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 the timing constraint (otherwise we say it is <SPAN CLASS="Definition">
violated</SPAN>
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).</P>
<P CLASS="Body">
<A NAME="pgfId=273190">
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In <A HREF="#26932" CLASS="XRef">
Table&nbsp;12.13</A>
 all instances in the critical path are inside instance <SPAN CLASS="BodyComputer">
v_1.u100</SPAN>
. Instance name <SPAN CLASS="BodyComputer">
u100</SPAN>
 is the new cell (cell name <SPAN CLASS="BodyComputer">
critical</SPAN>
) formed by merging six blocks in module <SPAN CLASS="BodyComputer">
viterbi</SPAN>
 (instance name <SPAN CLASS="BodyComputer">
v_1</SPAN>
).</P>
<P CLASS="Body">
<A NAME="pgfId=273200">
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The second column in <A HREF="#26932" CLASS="XRef">
Table&nbsp;12.13</A>
 shows the timing arc of the cell involved on the critical path. For example, <SPAN CLASS="BodyComputer">
CP --&gt; QN</SPAN>
 represents the path from the clock pin, <SPAN CLASS="BodyComputer">
CP</SPAN>
, to the flip-flop output pin, <SPAN CLASS="BodyComputer">
QN</SPAN>
, of a D flip-flop (cell name <SPAN CLASS="BodyComputer">
dfctnb</SPAN>
). The pin names and their functions come from the library data book. Each company adopts a different naming convention (in this case <SPAN CLASS="BodyComputer">
CP</SPAN>
 represents a positive clock edge, for example). The conventions are not always explicitly shown in the data books but are normally easy to discover by looking at examples. As another example, <SPAN CLASS="BodyComputer">
B0 --&gt; CO</SPAN>
 represents the path from the B input to the carry output of a 2-bit full adder (cell name <SPAN CLASS="BodyComputer">
ad02d1</SPAN>
).</P>
<P CLASS="Body">
<A NAME="pgfId=273235">
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The third column (<SPAN CLASS="BodyComputer">
incr</SPAN>
) represents the incremental delay contribution of the logic cell to the critical path.</P>
<P CLASS="Body">
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The fourth column (<SPAN CLASS="BodyComputer">
arrival</SPAN>
) shows the arrival time of the signal at the output pin of the logic cell. This is the cumulative delay to that point on the critical path.</P>
<P CLASS="Body">
<A NAME="pgfId=273238">
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The fifth column (<SPAN CLASS="BodyComputer">
trs</SPAN>
) describes whether the transition at the output node is rising (<SPAN CLASS="BodyComputer">
R</SPAN>
) or falling (<SPAN CLASS="BodyComputer">
F</SPAN>
). The timing analyzer examines each possible combination of rising and falling delays to find the critical path.</P>
<P CLASS="Body">
<A NAME="pgfId=273239">
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The sixth column (<SPAN CLASS="BodyComputer">
rampDel</SPAN>
) is a measure of the input slope (ramp delay, or slew rate). In submicron ASIC design this is an important contribution to delay. </P>
<P CLASS="Body">
<A NAME="pgfId=273244">
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The seventh column (<SPAN CLASS="BodyComputer">
Cap</SPAN>
) is the capacitance at the output node of the logic cell. This determines the logic cell delay and also the signal slew rate at the node. </P>
<P CLASS="Body">
<A NAME="pgfId=273245">
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The last column (<SPAN CLASS="BodyComputer">
cell</SPAN>
) is the cell name (from the cell-library data book). In this library suffix <SPAN CLASS="BodyComputer">
'd1'</SPAN>
 represents normal drive strength with <SPAN CLASS="BodyComputer">
'd0'</SPAN>
, <SPAN CLASS="BodyComputer">
'd2</SPAN>
', and <SPAN CLASS="BodyComputer">
'd5'</SPAN>
 being the other available strengths. </P>
<HR>
<DIV CLASS="footnotes">
<DIV CLASS="footnote">
<P CLASS="TableFootLast">
<SPAN CLASS="footnoteNumber">
1.</SPAN>
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See the text for explanations of the column headings.</P>
</DIV>
</DIV>
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