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</A>
—</P>
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<A NAME="pgfId=392330">
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1.3</P>
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<A NAME="pgfId=392332">
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12.0</P>
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<A NAME="pgfId=392334">
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—</P>
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<A NAME="pgfId=392336">
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12.0</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=392338">
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Totals</P>
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</A>
</P>
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</A>
</P>
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<A NAME="pgfId=392344">
</A>
</P>
</TD>
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<P CLASS="TableLast">
<A NAME="pgfId=392346">
</A>
</P>
</TD>
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<A NAME="pgfId=392348">
</A>
12</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLast">
<A NAME="pgfId=392350">
</A>
8</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLast">
<A NAME="pgfId=392352">
</A>
19.8</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLast">
<A NAME="pgfId=392354">
</A>
12.8</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLast">
<A NAME="pgfId=392356">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLast">
<A NAME="pgfId=392358">
</A>
189.6</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLast">
<A NAME="pgfId=392360">
</A>
122.4</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=326346">
</A>
<A HREF="#22837" CLASS="XRef">
Table 12.4</A>
lists the name, type, the number of transistors, the area, and the delay of each logic cell used in the hand-designed and synthesized comparator/MUX. We could have performed this analysis by hand using the cell-library data book and a calculator or spreadsheet, but it would have been tedious work—especially calculating the delays. The computer is excellent at this type of bookkeeping. We can think of the timing engine of a logic synthesizer as a logic calculator. </P>
<P CLASS="Body">
<A NAME="pgfId=326351">
</A>
We see from <A HREF="#22837" CLASS="XRef">
Table 12.4</A>
that the sum of the widths of all the cells used in the synthesized design (122.4 <SPAN CLASS="Symbol">
m</SPAN>
m) is less than for the hand design (189.6 <SPAN CLASS="Symbol">
m</SPAN>
m). All the standard cells in a library are the same height, 72 <SPAN CLASS="Symbol">
l</SPAN>
or 21.6 <SPAN CLASS="Symbol">
m</SPAN>
m, in this case. Thus the synthesized design is smaller. We could estimate the critical path of the hand design using the information from the cell-library data book (summarized in <A HREF="#22837" CLASS="XRef">
Table 12.4</A>
). Instead we will use the timing engine in the logic synthesizer as a logic calculator to extract the critical path for the hand-designed comparator/MUX. </P>
<P CLASS="Body">
<A NAME="pgfId=392377">
</A>
<A HREF="#31685" CLASS="XRef">
Table 12.5</A>
shows a timing analysis obtained by loading the hand-designed schematic netlist into the logic synthesizer. <A HREF="#31685" CLASS="XRef">
Table 12.5</A>
shows that the hand-designed (critical path 2.42 ns) and synthesized versions (critical path 2.43 ns) of the comparator/MUX are approximately the same speed. Remember, though, that we used the default settings during logic optimization. <A HREF="CH12.b.htm#22485" CLASS="XRef">
Section 12.11</A>
shows that the logic synthesizer can do much better.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="2">
<P CLASS="TableTitle">
<A NAME="pgfId=359894">
</A>
TABLE 12.5 <A NAME="31685">
</A>
Timing report for the hand-designed version of the comparator/MUX using the logic <BR>
synthesizer to calculate the critical path (compare with <A HREF="#23004" CLASS="XRef">
Table 12.3</A>
).</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=359898">
</A>
Command</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=359903">
</A>
Synthesizer output<A HREF="#pgfId=359902" CLASS="footnote">
7</A>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Computer">
<A NAME="pgfId=359993">
</A>
> report timing</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Computer">
<A NAME="pgfId=359995">
</A>
instance name </P>
<P CLASS="Computer">
<A NAME="pgfId=359996">
</A>
inPin --> outPin incr arrival trs rampDel cap cell </P>
<P CLASS="Computer">
<A NAME="pgfId=359997">
</A>
(ns) (ns) (ns) (pf) </P>
<P CLASS="Computer">
<A NAME="pgfId=359998">
</A>
---------------------------------------------------------------------- </P>
<P CLASS="Computer">
<A NAME="pgfId=360043">
</A>
a[1] .00 .00 F .00 .04 comp_mux </P>
<P CLASS="Computer">
<A NAME="pgfId=360044">
</A>
B1_i4</P>
<P CLASS="Computer">
<A NAME="pgfId=360045">
</A>
A1 --> ZN .61 .61 F .14 .03 xo02d1</P>
<P CLASS="Computer">
<A NAME="pgfId=360002">
</A>
B1_i3 </P>
<P CLASS="Computer">
<A NAME="pgfId=360003">
</A>
A2 --> ZN .85 1.46 F .19 .05 an04d1</P>
<P CLASS="Computer">
<A NAME="pgfId=360004">
</A>
B1_i5 </P>
<P CLASS="Computer">
<A NAME="pgfId=360005">
</A>
A --> ZN .42 1.88 F .23 .09 or03d1</P>
<P CLASS="Computer">
<A NAME="pgfId=360006">
</A>
B1_i6 </P>
<P CLASS="Computer">
<A NAME="pgfId=360007">
</A>
S --> Z .54 2.42 R .09 .02 mx21d1 </P>
<P CLASS="Computer">
<A NAME="pgfId=360008">
</A>
outp[0] .00 2.42 R .00 .00 comp_mux</P>
</TD>
</TR>
</TABLE>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=360634">
</A>
12.2.1 An Actel Version of the Comparator/MUX</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=360638">
</A>
<A HREF="#27840" CLASS="XRef">
Figure 12.4</A>
shows the results of targeting the comparator/MUX design to the Actel ACT 2/3 FPGA architecture. (The EDIF converter prefixes all internal nodes in this netlist with <SPAN CLASS="BodyComputer">
'block_0_DEF_NET_'</SPAN>
. This prefix was replaced with <SPAN CLASS="BodyComputer">
'n_'</SPAN>
in the Verilog file,<SPAN CLASS="FigureLabel">
</SPAN>
<SPAN CLASS="BodyComputer">
comp_mux_actel_o_adl_e.v</SPAN>
, derived from the <SPAN CLASS="BodyComputer">
.adl</SPAN>
netlist.) As can be seen by comparing the netlists and schematics in Figures <A HREF="#16015" CLASS="XRef">
12.3</A>
and <A HREF="#27840" CLASS="XRef">
12.4</A>
, the results are very different between a standard-cell library and the Actel library. Each of the symbols in the schematic in <A HREF="#27840" CLASS="XRef">
Figure 12.4</A>
represents the eight-input ACT 2/3 C-Module (see <A HREF="../../../../../../../../Prof.htm#18463" CLASS="XRef">
Figure 5.4</A>
a). The logic synthesizer, during the technology-mapping step, has decided which connections should be made to the inputs to the combinational logic macro, <SPAN CLASS="BodyComputer">
CM8</SPAN>
. The <SPAN CLASS="BodyComputer">
CM8</SPAN>
names and the ACT2/3 C-Module names (in parentheses) correspond as follows: <SPAN CLASS="BodyComputer">
S00(A0)</SPAN>
, <SPAN CLASS="BodyComputer">
S01(B0)</SPAN>
, <SPAN CLASS="BodyComputer">
S10(A1)</SPAN>
, <SPAN CLASS="BodyComputer">
S11(A2)</SPAN>
, <SPAN CLASS="BodyComputer">
D0(D00)</SPAN>
, <SPAN CLASS="BodyComputer">
D1(D01)</SPAN>
, <SPAN CLASS="BodyComputer">
D2(D10)</SPAN>
, <SPAN CLASS="BodyComputer">
D3(D11)</SPAN>
, and <SPAN CLASS="BodyComputer">
Y(Y)</SPAN>
.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Computer">
<A NAME="pgfId=394895">
</A>
`timescale 1 ns/100 ps</P>
<P CLASS="Computer">
<A NAME="pgfId=394896">
</A>
<B CLASS="Keyword">
module</B>
comp_mux_actel_o (a, b, outp);</P>
<P CLASS="Computer">
<A NAME="pgfId=394897">
</A>
<B CLASS="Keyword">
input</B>
[2:0] a, b; <B CLASS="Keyword">
output</B>
[2:0] outp;</P>
<P CLASS="Computer">
<A NAME="pgfId=394898">
</A>
<B CLASS="Keyword">
wire</B>
n_13, n_17, n_19, n_21, n_23, n_27, n_29, n_31, n_62;</P>
<P CLASS="Computer">
<A NAME="pgfId=394899">
</A>
</P>
<P CLASS="Computer">
<A NAME="pgfId=394900">
</A>
CM8 I_5_CM8(.D0(n_31), .D1(n_62), .D2(a[0]), .D3(n_62), .S00(n_62), .S01(n_13), .S10(n_23), .S11(n_21), .Y(outp[0]));</P>
<P CLASS="Computer">
<A NAME="pgfId=394901">
</A>
CM8 I_2_CM8(.D0(n_31), .D1(n_19), .D2(n_62), .D3(n_62), .S00(n_62), .S01(b[1]), .S10(n_31), .S11(n_17), .Y(outp[1])); </P>
<P CLASS="Computer">
<A NAME="pgfId=394902">
</A>
CM8 I_1_CM8(.D0(n_31), .D1(n_31), .D2(b[2]), .D3(n_31), .S00(n_62), .S01(n_31), .S10(n_31), .S11(a[2]), .Y(outp[2]));</P>
<P CLASS="Computer">
<A NAME="pgfId=394903">
</A>
VCC VCC_I(.Y(n_62));</P>
<P CLASS="Computer">
<A NAME="pgfId=394904">
</A>
CM8 I_4_CM8(.D0(a[2]), .D1(n_31), .D2(n_62), .D3(n_62), .S00(n_62), .S01(b[2]), .S10(n_31), .S11(a[1]), .Y(n_19));</P>
<P CLASS="Computer">
<A NAME="pgfId=394905">
</A>
CM8 I_7_CM8(.D0(b[1]), .D1(b[2]), .D2(n_31), .D3(n_31), .S00(a[2]), .S01(b[1]), .S10(n_31), .S11(a[1]), .Y(n_23));</P>
<P CLASS="Computer">
<A NAME="pgfId=394906">
</A>
CM8 I_9_CM8(.D0(n_31), .D1(n_31), .D2(a[1]), .D3(n_31), .S00(n_62), .S01(b[1]), .S10(n_31), .S11(b[0]), .Y(n_27));</P>
<P CLASS="Computer">
<A NAME="pgfId=394907">
</A>
CM8 I_8_CM8(.D0(n_29), .D1(n_62), .D2(n_31), .D3(a[2]), .S00(n_62), .S01(n_27), .S10(n_31), .S11(b[2]), .Y(n_13));</P>
<P CLASS="Computer">
<A NAME="pgfId=394908">
</A>
CM8 I_3_CM8(.D0(n_31), .D1(n_31), .D2(a[1]), .D3(n_31), .S00(n_62), .S01(a[2]), .S10(n_31), .S11(b[2]), .Y(n_17));</P>
<P CLASS="Computer">
<A NAME="pgfId=394909">
</A>
CM8 I_6_CM8(.D0(b[2]), .D1(n_31), .D2(n_62), .D3(n_62), .S00(n_62), .S01(a[2]), .S10(n_31), .S11(b[0]), .Y(n_21));</P>
<P CLASS="Computer">
<A NAME="pgfId=394910">
</A>
CM8 I_10_CM8(.D0(n_31), .D1(n_31), .D2(b[0]), .D3(n_31), .S00(n_62), .S01(n_31), .S10(n_31), .S11(a[2]), .Y(n_29));</P>
<P CLASS="Computer">
<A NAME="pgfId=394911">
</A>
GND GND_I(.Y(n_31));</P>
<P CLASS="Computer">
<A NAME="pgfId=394912">
</A>
<B CLASS="Keyword">
endmodule</B>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=394917">
</A>
</P>
<DIV>
<IMG SRC="CH12-4.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="2">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=394920">
</A>
FIGURE 12.4 <A NAME="27840">
</A>
<SPAN CLASS="FigureLabel">
The Actel version of the comparator/MUX after logic optimization. This figure shows the s</SPAN>
tructural netlist, <SPAN CLASS="BodyComputer">
comp_mux_actel_o_adl_e.v</SPAN>
, and its derived schematic.</P>
</TD>
</TR>
</TABLE>
</DIV>
<HR>
<DIV CLASS="footnotes">
<DIV CLASS="footnote">
<P CLASS="TableFootLast">
<SPAN CLASS="footnoteNumber">
1.</SPAN>
<A NAME="pgfId=250098">
</A>
<SPAN CLASS="BodyComputer">
Cell Name</SPAN>
<A NAME="31398">
</A>
= cell name from the ASIC library (Compass Passport, 0.6 <SPAN CLASS="Symbol">
m</SPAN>
m high-density, 5 V standard-cell library, cb60hd230); <SPAN CLASS="BodyComputer">
Num Insts</SPAN>
= number of cell instances; Gate Count Per Cell = equivalent gates with two-input NAND = 1 gate (with number of transistors <SPAN CLASS="Symbol">
ª</SPAN>
equivalent gates <SPAN CLASS="Symbol">
¥</SPAN>
4); Width Per Cell = width in <SPAN CLASS="Symbol">
m</SPAN>
m (cell height in this library is 72<SPAN CLASS="Symbol">
l</SPAN>
or 21.6<SPAN CLASS="Symbol">
m</SPAN>
m); <SPAN CLASS="BodyComputer">
incr</SPAN>
= incremental delay time due to logic cell delay; <SPAN CLASS="BodyComputer">
trs</SPAN>
= transition; <SPAN CLASS="BodyComputer">
R</SPAN>
= rising; <SPAN CLASS="BodyComputer">
F</SPAN>
= falling; <SPAN CLASS="BodyComputer">
rampDel</SPAN>
= ramp delay; <SPAN CLASS="BodyComputer">
cap</SPAN>
= capacitance at node or cell output pin.</P>
</DIV>
<DIV CLASS="footnote">
<P CLASS="TableFootnote">
<SPAN CLASS="footnoteNumber">
2.</SPAN>
<A NAME="pgfId=392056">
</A>
0.6 <SPAN CLASS="Symbol">
m</SPAN>
m, 5 V, high-density Compass standard-cell library, cb60hd230.</P>
</DIV>
<DIV CLASS="footnote">
<P CLASS="TableFootnote">
<SPAN CLASS="footnoteNumber">
3.</SPAN>
<A NAME="pgfId=392060">
</A>
Average over all inputs with load capacitance equal to two standard loads (one standard load = 0.016 pF).</P>
</DIV>
<DIV CLASS="footnote">
<P CLASS="TableFootnote">
<SPAN CLASS="footnoteNumber">
4.</SPAN>
<A NAME="pgfId=392067">
</A>
2-input NAND = 1 gate equivalent.</P>
</DIV>
<DIV CLASS="footnote">
<P CLASS="TableFootnote">
<SPAN CLASS="footnoteNumber">
5.</SPAN>
<A NAME="pgfId=392084">
</A>
Cell height is 72<SPAN CLASS="Symbol">
l</SPAN>
(21.6<SPAN CLASS="Symbol">
m</SPAN>
m).</P>
</DIV>
<DIV CLASS="footnote">
<P CLASS="TableFootLast">
<SPAN CLASS="footnoteNumber">
6.</SPAN>
<A NAME="pgfId=392315">
</A>
Rise and fall delays are different for the two inputs, A and B, of this cell: t <SUB CLASS="Subscript">
PLHA</SUB>
= 0.48 ns; t <SUB CLASS="Subscript">
PLHB</SUB>
= 0.36 ns; t <SUB CLASS="Subscript">
PHLA</SUB>
= 0.59 ns; t <SUB CLASS="Subscript">
PHLB</SUB>
= 0.33 ns.</P>
</DIV>
<DIV CLASS="footnote">
<P CLASS="TableFootLast">
<SPAN CLASS="footnoteNumber">
7.</SPAN>
<A NAME="pgfId=359902">
</A>
See footnote <A HREF="#31398" CLASS="XRef">
1</A>
in <A HREF="#23004" CLASS="XRef">
Table 12.3</A>
for explanations of the abbreviations used in this table.</P>
</DIV>
</DIV>
<HR><P>[ <A HREF="CH12.htm">Chapter start</A> ] [ <A HREF="CH12.1.htm">Previous page</A> ] [ <A HREF="CH12.3.htm">Next page</A> ]</P></BODY>
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