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<TITLE> 12.2 A Comparator/MUX</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
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<P>[ <A HREF="CH12.htm">Chapter start</A> ] [ <A HREF="CH12.1.htm">Previous page</A> ] [ <A HREF="CH12.3.htm">Next page</A> ]</P><!--#include file="AmazonAsic.html"--><HR></DIV>
<H1 CLASS="Heading1">
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12.2 <A NAME="11737">
</A>
A Comparator/MUX</H1>
<P CLASS="BodyAfterHead">
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With the Verilog behavioral model of <A HREF="CH12.1.htm#40122" CLASS="XRef">
Figure 12.1</A>
as the input, logic-synthesis software generates logic that performs the same function as the Verilog. The software then optimizes the logic to produce a structural model, which references logic cells from the cell library and details their connections. </P>
<TABLE>
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`timescale 1ns / 10ps</P>
<P CLASS="Computer">
<A NAME="pgfId=394945">
</A>
<B CLASS="Keyword">
module</B>
comp_mux_u (a, b, outp);</P>
<P CLASS="Computer">
<A NAME="pgfId=394946">
</A>
<B CLASS="Keyword">
input</B>
[2:0] a; <B CLASS="Keyword">
input</B>
[2:0] b;</P>
<P CLASS="Computer">
<A NAME="pgfId=394947">
</A>
<B CLASS="Keyword">
output</B>
[2:0] outp;</P>
<P CLASS="Computer">
<A NAME="pgfId=394948">
</A>
<B CLASS="Keyword">
supply1</B>
VDD; <B CLASS="Keyword">
supply0</B>
VSS;</P>
<P CLASS="Computer">
<A NAME="pgfId=394949">
</A>
</P>
<P CLASS="Computer">
<A NAME="pgfId=394950">
</A>
in01d0 u2 (.I(b[1]), .ZN(u2_ZN));</P>
<P CLASS="Computer">
<A NAME="pgfId=394951">
</A>
nd02d0 u3 (.A1(a[1]), .A2(u2_ZN), .ZN(u3_ZN));</P>
<P CLASS="Computer">
<A NAME="pgfId=394952">
</A>
in01d0 u4 (.I(a[1]), .ZN(u4_ZN));</P>
<P CLASS="Computer">
<A NAME="pgfId=394953">
</A>
nd02d0 u5 (.A1(u4_ZN), .A2(b[1]), .ZN(u5_ZN));</P>
<P CLASS="Computer">
<A NAME="pgfId=394954">
</A>
in01d0 u6 (.I(a[0]), .ZN(u6_ZN));</P>
<P CLASS="Computer">
<A NAME="pgfId=394955">
</A>
nd02d0 u7 (.A1(u6_ZN), .A2(u3_ZN), .ZN(u7_ZN));</P>
<P CLASS="Computer">
<A NAME="pgfId=394956">
</A>
nd02d0 u8 (.A1(b[0]), .A2(u3_ZN), .ZN(u8_ZN));</P>
<P CLASS="Computer">
<A NAME="pgfId=394957">
</A>
nd03d0 u9 (.A1(u5_ZN), .A2(u7_ZN), .A3(u8_ZN), .ZN(u9_ZN));</P>
<P CLASS="Computer">
<A NAME="pgfId=394958">
</A>
in01d0 u10 (.I(a[2]), .ZN(u10_ZN));</P>
<P CLASS="Computer">
<A NAME="pgfId=394959">
</A>
nd02d0 u11 (.A1(u10_ZN), .A2(u9_ZN), .ZN(u11_ZN));</P>
<P CLASS="Computer">
<A NAME="pgfId=394960">
</A>
nd02d0 u12 (.A1(b[2]), .A2(u9_ZN), .ZN(u12_ZN));</P>
<P CLASS="Computer">
<A NAME="pgfId=394961">
</A>
nd02d0 u13 (.A1(u10_ZN), .A2(b[2]), .ZN(u13_ZN));</P>
<P CLASS="Computer">
<A NAME="pgfId=394962">
</A>
nd03d0 u14 (.A1(u11_ZN), .A2(u12_ZN), .A3(u13_ZN), .ZN(u14_ZN));</P>
<P CLASS="Computer">
<A NAME="pgfId=394963">
</A>
nd02d0 u15 (.A1(a[2]), .A2(u14_ZN), .ZN(u15_ZN));</P>
<P CLASS="Computer">
<A NAME="pgfId=394964">
</A>
in01d0 u16 (.I(u14_ZN), .ZN(u16_ZN));</P>
<P CLASS="Computer">
<A NAME="pgfId=394965">
</A>
nd02d0 u17 (.A1(b[2]), .A2(u16_ZN), .ZN(u17_ZN));</P>
<P CLASS="Computer">
<A NAME="pgfId=394966">
</A>
nd02d0 u18 (.A1(u15_ZN), .A2(u17_ZN), .ZN(outp[2]));</P>
<P CLASS="Computer">
<A NAME="pgfId=394967">
</A>
nd02d0 u19 (.A1(a[1]), .A2(u14_ZN), .ZN(u19_ZN));</P>
<P CLASS="Computer">
<A NAME="pgfId=394968">
</A>
nd02d0 u20 (.A1(b[1]), .A2(u16_ZN), .ZN(u20_ZN));</P>
<P CLASS="Computer">
<A NAME="pgfId=394969">
</A>
nd02d0 u21 (.A1(u19_ZN), .A2(u20_ZN), .ZN(outp[1]));</P>
<P CLASS="Computer">
<A NAME="pgfId=394970">
</A>
nd02d0 u22 (.A1(a[0]), .A2(u14_ZN), .ZN(u22_ZN));</P>
<P CLASS="Computer">
<A NAME="pgfId=394971">
</A>
nd02d0 u23 (.A1(b[0]), .A2(u16_ZN), .ZN(u23_ZN));</P>
<P CLASS="Computer">
<A NAME="pgfId=394972">
</A>
nd02d0 u24 (.A1(u22_ZN), .A2(u23_ZN), .ZN(outp[0]));</P>
<P CLASS="Computer">
<A NAME="pgfId=394973">
</A>
</P>
<P CLASS="Computer">
<A NAME="pgfId=394974">
</A>
<B CLASS="Keyword">
endmodule</B>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=394979">
</A>
</P>
<DIV>
<IMG SRC="CH12-2.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="2">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=394982">
</A>
FIGURE 12.2 <A NAME="22754">
</A>
The comparator/MUX after logic synthesis, but before logic optimization. This figure shows the structural netlist, <SPAN CLASS="BodyComputer">
comp_mux_u.v</SPAN>
, and its derived schematic.</P>
</TD>
</TR>
</TABLE>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=394987">
</A>
</P>
<P CLASS="Computer">
<A NAME="pgfId=394988">
</A>
</P>
<P CLASS="Computer">
<A NAME="pgfId=394989">
</A>
</P>
<P CLASS="Computer">
<A NAME="pgfId=394990">
</A>
`timescale 1ns / 10ps</P>
<P CLASS="Computer">
<A NAME="pgfId=394991">
</A>
<B CLASS="Keyword">
module</B>
comp_mux_o (a, b, outp);</P>
<P CLASS="Computer">
<A NAME="pgfId=394992">
</A>
<B CLASS="Keyword">
input</B>
[2:0] a; <B CLASS="Keyword">
input</B>
[2:0] b;</P>
<P CLASS="Computer">
<A NAME="pgfId=394993">
</A>
<B CLASS="Keyword">
output</B>
[2:0] outp;</P>
<P CLASS="Computer">
<A NAME="pgfId=394994">
</A>
<B CLASS="Keyword">
supply1</B>
VDD; <B CLASS="Keyword">
supply0</B>
VSS;</P>
<P CLASS="Computer">
<A NAME="pgfId=394995">
</A>
</P>
<P CLASS="Computer">
<A NAME="pgfId=394996">
</A>
in01d0 B1_i1 (.I(a[2]), .ZN(B1_i1_ZN));</P>
<P CLASS="Computer">
<A NAME="pgfId=394997">
</A>
in01d0 B1_i2 (.I(b[1]), .ZN(B1_i2_ZN));</P>
<P CLASS="Computer">
<A NAME="pgfId=394998">
</A>
oa01d1 B1_i3 (.A1(a[0]), .A2(B1_i4_ZN), .B1(B1_i2_ZN), .B2(a[1]), .ZN(B1_i3_Z;</P>
<P CLASS="Computer">
<A NAME="pgfId=394999">
</A>
fn05d1 B1_i4 (.A1(a[1]), .B1(b[1]), .ZN(B1_i4_ZN));</P>
<P CLASS="Computer">
<A NAME="pgfId=395000">
</A>
fn02d1 B1_i5 (.A(B1_i3_ZN), .B(B1_i1_ZN), .C(b[2]), .ZN(B1_i5_ZN));</P>
<P CLASS="Computer">
<A NAME="pgfId=395001">
</A>
mx21d1 B1_i6 (.I0(a[0]), .I1(b[0]), .S(B1_i5_ZN), .Z(outp[0]));</P>
<P CLASS="Computer">
<A NAME="pgfId=395002">
</A>
mx21d1 B1_i7 (.I0(a[1]), .I1(b[1]), .S(B1_i5_ZN), .Z(outp[1]));</P>
<P CLASS="Computer">
<A NAME="pgfId=395003">
</A>
mx21d1 B1_i8 (.I0(a[2]), .I1(b[2]), .S(B1_i5_ZN), .Z(outp[2]));</P>
<P CLASS="Computer">
<A NAME="pgfId=395004">
</A>
</P>
<P CLASS="Computer">
<A NAME="pgfId=395005">
</A>
<B CLASS="Keyword">
endmodule</B>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=395010">
</A>
</P>
<DIV>
<IMG SRC="CH12-3.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="2">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=395012">
</A>
FIGURE 12.3 <A NAME="16015">
</A>
The comparator/MUX after logic synthesis and logic optimization with the default settings. This figure shows the structural netlist, <SPAN CLASS="BodyComputer">
comp_mux_o.v</SPAN>
, and its derived schematic.</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=394797">
</A>
Before running a logic synthesizer, it is necessary to set up paths and startup files (<SPAN CLASS="BodyComputer">
synopsys_dc.setup</SPAN>
, <SPAN CLASS="BodyComputer">
compass.boo</SPAN>
, <SPAN CLASS="BodyComputer">
view.ini</SPAN>
, or similar). These files set the target library and directory locations. Normally it is easier to run logic synthesis in text mode using a script. A <SPAN CLASS="Definition">
script</SPAN>
<A NAME="marker=394798">
</A>
is a text file that directs a software tool to execute a series of synthesis commands (we call this a <SPAN CLASS="Definition">
synthesis run</SPAN>
<A NAME="marker=394799">
</A>
). <A HREF="#22754" CLASS="XRef">
Figure 12.2</A>
shows a structural netlist, <SPAN CLASS="BodyComputer">
comp_mux_u.v</SPAN>
, and the derived schematic after logic synthesis, but before any <SPAN CLASS="Emphasis">
logic</SPAN>
<SPAN CLASS="Emphasis">
optimization</SPAN>
. A <SPAN CLASS="Definition">
derived schematic</SPAN>
<A NAME="marker=394805">
</A>
is created by software from a structural netlist (as opposed to a schematic drawn by hand). <BR>
shows the structural netlist, <SPAN CLASS="BodyComputer">
comp_mux_o.v</SPAN>
, and the derived schematic after logic optimization is performed (with the default settings). Figures <A HREF="#22754" CLASS="XRef">
12.2</A>
and <A HREF="#16015" CLASS="XRef">
12.3</A>
show the results of the two separate steps: logic synthesis and logic optimization. Confusingly, the whole process, which includes synthesis and optimization (and other steps as well), is referred to as <SPAN CLASS="Emphasis">
logic synthesis</SPAN>
. We also refer to the software that performs all of these steps (even if the software consists of more than one program) as a <SPAN CLASS="Emphasis">
logic synthesizer</SPAN>
. </P>
<P CLASS="Body">
<A NAME="pgfId=394794">
</A>
Logic synthesis parses (in a process sometimes called <SPAN CLASS="Definition">
analysis</SPAN>
<A NAME="marker=353853">
</A>
) and translates (sometimes called <SPAN CLASS="Definition">
elaboration</SPAN>
<A NAME="marker=353849">
</A>
) the input HDL to a data structure. This data structure is then converted to a network of generic logic cells. For example, the network in <A HREF="#22754" CLASS="XRef">
Figure 12.2</A>
uses NAND gates (each with three or fewer inputs in this case) and inverters. This network of generic logic cells is technology-independent since cell libraries in any technology normally contain NAND gates and inverters. The next step, <SPAN CLASS="Definition">
logic optimization</SPAN>
<A NAME="marker=254404">
</A>
, attempts to improve this technology-independent network under the controls of the designer. The output of the optimization step is an optimized, but still technology-independent, network. Finally, in the <SPAN CLASS="Definition">
logic-mapping</SPAN>
<A NAME="marker=253170">
</A>
step, the synthesizer maps the optimized logic to a specified technology-dependent target cell library. <A HREF="#16015" CLASS="XRef">
Figure 12.3</A>
shows the results of using a standard-cell library as the target.</P>
<P CLASS="Body">
<A NAME="pgfId=250084">
</A>
Text reports such as the one shown in <A HREF="#23004" CLASS="XRef">
Table 12.3</A>
may be the only output that the designer sees from the logic-synthesis tool. Often, synthesized ASIC netlists and the derived schematics containing thousands of logic cells are far too large to follow. To make things even more difficult, the net names and instance names in synthesized netlists are automatically generated. This makes it hard to see which lines of code in the HDL generated which logic cells in the synthesized netlist or derived schematic.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="2">
<P CLASS="TableTitle">
<A NAME="pgfId=250090">
</A>
TABLE 12.3 <A NAME="23004">
</A>
Reports from the logic synthesizer for the Verilog version of the comparator/MUX.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=250094">
</A>
Command</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=250099">
</A>
Synthesizer output<A HREF="#pgfId=250098" CLASS="footnote">
1</A>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Computer">
<A NAME="pgfId=250101">
</A>
> synthesize</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Computer">
<A NAME="pgfId=250104">
</A>
Num Gate Count Tot Gate Width Total</P>
<P CLASS="Computer">
<A NAME="pgfId=250105">
</A>
Cell Name Insts Per Cell Count Per Cell Width</P>
<P CLASS="Computer">
<A NAME="pgfId=250106">
</A>
--------- ----- ---------- -------- -------- --------</P>
<P CLASS="Computer">
<A NAME="pgfId=250107">
</A>
in01d0 5 .8 3.8 7.2 36.0</P>
<P CLASS="Computer">
<A NAME="pgfId=250108">
</A>
nd02d0 16 1.0 16.0 9.6 153.6</P>
<P CLASS="Computer">
<A NAME="pgfId=250109">
</A>
nd03d0 2 1.3 2.5 12.0 24.0</P>
<P CLASS="Computer">
<A NAME="pgfId=250110">
</A>
--------- ----- ---------- -------- -------- --------</P>
<P CLASS="Computer">
<A NAME="pgfId=250111">
</A>
Totals: 23 22.2 213.6</P>
<P CLASS="Computer">
<A NAME="pgfId=298417">
</A>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Computer">
<A NAME="pgfId=250113">
</A>
> optimize</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Computer">
<A NAME="pgfId=250116">
</A>
Num Gate Count Tot Gate Width Total</P>
<P CLASS="Computer">
<A NAME="pgfId=250117">
</A>
Cell Name Insts Per Cell Count Per Cell Width</P>
<P CLASS="Computer">
<A NAME="pgfId=250118">
</A>
--------- ----- ---------- -------- -------- --------</P>
<P CLASS="Computer">
<A NAME="pgfId=250119">
</A>
fn02d1 1 1.8 1.8 16.8 16.8</P>
<P CLASS="Computer">
<A NAME="pgfId=250120">
</A>
fn05d1 1 1.3 1.3 12.0 12.0</P>
<P CLASS="Computer">
<A NAME="pgfId=250121">
</A>
in01d0 2 .8 1.5 7.2 14.4</P>
<P CLASS="Computer">
<A NAME="pgfId=250122">
</A>
mx21d1 3 2.2 6.8 21.6 64.8</P>
<P CLASS="Computer">
<A NAME="pgfId=250123">
</A>
oa01d1 1 1.5 1.5 14.4 14.4</P>
<P CLASS="Computer">
<A NAME="pgfId=250124">
</A>
--------- ----- ---------- -------- -------- --------</P>
<P CLASS="Computer">
<A NAME="pgfId=250125">
</A>
Totals: 8 12.8 122.4</P>
<P CLASS="Computer">
<A NAME="pgfId=298418">
</A>
</P>
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