📄 ch12.7.htm
字号:
Std_logic; yOut: <B CLASS="Keyword">
out</B>
Std_logic);</P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=4356">
</A>
<B CLASS="Keyword">
end</B>
SM1;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4366">
</A>
<B CLASS="Keyword">
architecture</B>
Moore <B CLASS="Keyword">
of</B>
SM1 <B CLASS="Keyword">
is</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4368">
</A>
<B CLASS="Keyword">
type</B>
state <B CLASS="Keyword">
is</B>
(s1, s2, s3, s4);</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4370">
</A>
<B CLASS="Keyword">
signal</B>
pS, nS : state;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4372">
</A>
<B CLASS="Keyword">
begin</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4374">
</A>
<B CLASS="Keyword">
process </B>
(aIn, pS) <B CLASS="Keyword">
begin</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4376">
</A>
<B CLASS="Keyword">
case</B>
pS <B CLASS="Keyword">
is</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4378">
</A>
<B CLASS="Keyword">
when</B>
s1 => yOut <= '0'; nS <= s4;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4380">
</A>
<B CLASS="Keyword">
when</B>
s2 => yOut <= '1'; nS <= s3;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4382">
</A>
<B CLASS="Keyword">
when</B>
s3 => yOut <= '1'; nS <= s1;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4384">
</A>
<B CLASS="Keyword">
when</B>
s4 => yOut <= '1'; nS <= s2;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4386">
</A>
<B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
case</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4388">
</A>
<B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
process</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4390">
</A>
<B CLASS="Keyword">
process</B>
<B CLASS="Keyword">
begin</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=288042">
</A>
-- synopsys etc.</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4392">
</A>
--compass Statemachine adj pS</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4394">
</A>
<B CLASS="Keyword">
wait</B>
<B CLASS="Keyword">
until</B>
clk = '1'; pS <= nS;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4398">
</A>
<B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
process</B>
;</P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=4400">
</A>
<B CLASS="Keyword">
end</B>
Moore;</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=4408">
</A>
An example input, <SPAN CLASS="BodyComputer">
aIn</SPAN>
, is included but not used in the next state assignments. A reset is also omitted to further simplify this example.</P>
<P CLASS="Body">
<A NAME="pgfId=294465">
</A>
An FSM compiler <SPAN CLASS="Definition">
extracts</SPAN>
<A NAME="marker=294478">
</A>
the state machine. Some companies use FSM compilers that are separate from the logic synthesizers (and priced separately) because the algorithms for FSM optimization are different from those for optimizing combinational logic. We can see what is happening by asking the Compass synthesizer to write out intermediate results. The synthesizer extracts the FSM and produces the following output in a state-machine language used by the tools:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=288465">
</A>
sm sm1_ps_sm;</P>
<P CLASS="Computer">
<A NAME="pgfId=288063">
</A>
inputs; outputs yout_smo; clock clk;</P>
<P CLASS="Computer">
<A NAME="pgfId=288130">
</A>
STATE S1 { let yout_smo=0 ; } --> S4;</P>
<P CLASS="Computer">
<A NAME="pgfId=288131">
</A>
STATE S2 { let yout_smo=1 ; } --> S3;</P>
<P CLASS="Computer">
<A NAME="pgfId=288084">
</A>
STATE S3 { let yout_smo=1 ; } --> S1;</P>
<P CLASS="Computer">
<A NAME="pgfId=288091">
</A>
STATE S4 { let yout_smo=1 ; } --> S2;</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=288058">
</A>
end</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=288179">
</A>
You can use this language to modify the FSM and then use this modified code as an input to the synthesizer if you wish. In our case, it serves as documentation that explains the FSM behavior.</P>
<P CLASS="Body">
<A NAME="pgfId=294479">
</A>
Using one-hot encoding generates the following structural Verilog netlist (<SPAN CLASS="BodyComputer">
dfntnb</SPAN>
is positive-edge–triggered D flip-flop, and <SPAN CLASS="BodyComputer">
nd03d0</SPAN>
is a three-input NAND):</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=288472">
</A>
dfntnb sm_ps4(.D(sm_ps1_Q),.CP(clk),.Q(sm_ps4_Q),.QN(sm_ps4_QN));</P>
<P CLASS="Computer">
<A NAME="pgfId=288473">
</A>
dfntnb sm_ps3(.D(sm_ps2_Q),.CP(clk),.Q(sm_ps3_Q),.QN(sm_ps3_QN));</P>
<P CLASS="Computer">
<A NAME="pgfId=288474">
</A>
dfntnb sm_ps2(.D(sm_ps4_Q),.CP(clk),.Q(sm_ps2_Q),.QN(sm_ps2_QN));</P>
<P CLASS="Computer">
<A NAME="pgfId=288475">
</A>
dfntnb sm_ps1(.D(sm_ps3_Q),.CP(clk),.Q(sm_ps1_Q),.QN(\sm_ps1.QN ));</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=288476">
</A>
nd03d0 i_6(.A1(sm_ps4_QN),.A2(sm_ps3_QN),.A3(sm_ps2_QN), .ZN(yout_smo));</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=288250">
</A>
(Each example shows only the logic cells and their interconnection in the Verilog structural netlists.) The synthesizer has assigned one flip-flop to each of the four states to form a 4-bit state register. The FSM output (renamed from <SPAN CLASS="BodyComputer">
yOut</SPAN>
to <SPAN CLASS="BodyComputer">
yout_smo</SPAN>
by the software) is taken from the output of the three-input NAND gate that decodes the outputs from the flip-flops in the state register. </P>
<P CLASS="Body">
<A NAME="pgfId=294376">
</A>
Using adjacent encoding gives a simpler result,</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=288494">
</A>
dfntnb sm_ps2(.D(i_4_ZN),.CP(clk), .Q(\sm_ps2.Q ),.QN(sm_ps2_QN));</P>
<P CLASS="Computer">
<A NAME="pgfId=288495">
</A>
dfntnb sm_ps1(.D(sm_ps1_QN),.CP(clk),.Q(\sm_ps1.Q ),.QN(sm_ps1_QN));</P>
<P CLASS="Computer">
<A NAME="pgfId=288496">
</A>
oa04d1 i_4(.A1(sm_ps1_QN),.A2(sm_ps2_QN),.B(yout_smo),.ZN(i_4_ZN));</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=288180">
</A>
nd02d0 i_5(.A1(sm_ps2_QN), .A2(sm_ps1_QN), .ZN(yout_smo));</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=288052">
</A>
(<SPAN CLASS="BodyComputer">
oa04d1</SPAN>
is an OAI21 logic cell, <SPAN CLASS="BodyComputer">
nd02d0</SPAN>
is a two-input NAND). In this case binary encoding for the four states uses only two flip-flops. The two-input NAND gate decodes the states to produce the output. The OAI21 logic cell implements the logic that determines the next state. The combinational logic in this example is only slightly more complex than that for the one-hot encoding, but, in general, combinational logic for one-hot encoding is simpler than the other forms of encoding. </P>
<P CLASS="Body">
<A NAME="pgfId=294379">
</A>
Using the option <SPAN CLASS="BodyComputer">
'moore'</SPAN>
for Moore encoding, we receive the following message from the FSM compiler:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=288198">
</A>
The states were assigned these codes:</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=288199">
</A>
0?? : S1 100 : S2 101 : S3 110 : S4</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=288343">
</A>
The FSM compiler has assigned three bits to the state register. The first bit in the state register is used as the output. We can see more clearly what has happened by looking at the Verilog structural netlist:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=294242">
</A>
dfntnb sm_ps3(.D(i_6_ZN),.CP(clk),.Q(yout_smo),.QN(sm_ps3_QN));</P>
<P CLASS="Computer">
<A NAME="pgfId=294243">
</A>
dfntnb sm_ps2(.D(sm_ps3_QN),.CP(clk),.Q(sm_ps2_Q),.QN(\sm_ps2.QN ));</P>
<P CLASS="Computer">
<A NAME="pgfId=294244">
</A>
dfntnb sm_ps1(.D(i_5_ZN),.CP(clk),.Q(sm_ps1_Q),.QN(\sm_ps1.QN ));</P>
<P CLASS="Computer">
<A NAME="pgfId=294245">
</A>
nr02d0 i_5(.A1(sm_ps3_QN),.A2(sm_ps2_Q),.ZN(i_5_ZN));</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=294246">
</A>
nd02d0 i_6(.A1(sm_ps1_Q),.A2(yout_smo),.ZN(i_6_ZN));</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=294414">
</A>
The output, <SPAN CLASS="BodyComputer">
yout_smo</SPAN>
, is now taken directly from a flip-flop. This means that the output appears after the clock edge with no combinational logic delay (only the clock-to-Q delay). This is useful for FSMs that are required to produce outputs as soon as possible after the active clock edge (in <A NAME="marker=395361">
</A>
PCI bus controllers, for example).</P>
<P CLASS="Body">
<A NAME="pgfId=288346">
</A>
The following code is a template for a <A NAME="marker=288345">
</A>
Mealy state machine:</P>
<P CLASS="ComputerFirstLabel">
<A NAME="pgfId=288512">
</A>
<B CLASS="Keyword">
library</B>
IEEE; <B CLASS="Keyword">
use</B>
IEEE.STD_LOGIC_1164.<B CLASS="Keyword">
all</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=288513">
</A>
<B CLASS="Keyword">
entity</B>
SM2 <B CLASS="Keyword">
is</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=288514">
</A>
<B CLASS="Keyword">
port</B>
(aIn, clk : <B CLASS="Keyword">
in</B>
Std_logic; yOut: <B CLASS="Keyword">
out</B>
Std_logic);</P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=288515">
</A>
<B CLASS="Keyword">
end</B>
SM2;</P>
<P CLASS="ComputerFirstLabel">
<A NAME="pgfId=4410">
</A>
<B CLASS="Keyword">
architecture</B>
Mealy <B CLASS="Keyword">
of</B>
SM2 <B CLASS="Keyword">
is</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4412">
</A>
<B CLASS="Keyword">
type</B>
state <B CLASS="Keyword">
is</B>
(s1, s2, s3, s4);</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4414">
</A>
<B CLASS="Keyword">
signal</B>
pS, nS : state;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4416">
</A>
<B CLASS="Keyword">
begin</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4418">
</A>
<B CLASS="Keyword">
process</B>
(aIn, pS) <B CLASS="Keyword">
begin</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4420">
</A>
<B CLASS="Keyword">
case</B>
pS <B CLASS="Keyword">
is</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4422">
</A>
<B CLASS="Keyword">
when</B>
s1 => <B CLASS="Keyword">
if</B>
(aIn = '1') </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4424">
</A>
<B CLASS="Keyword">
then</B>
yOut <= '0'; nS <= s4;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4426">
</A>
<B CLASS="Keyword">
else</B>
yOut <= '1'; nS <= s3;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4428">
</A>
<B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
if</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4430">
</A>
<B CLASS="Keyword">
when</B>
s2 => yOut <= '1'; nS <= s3;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4432">
</A>
<B CLASS="Keyword">
when</B>
s3 => yOut <= '1'; nS <= s1;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4434">
</A>
<B CLASS="Keyword">
when</B>
s4 => <B CLASS="Keyword">
if</B>
(aIn = '1')</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4436">
</A>
<B CLASS="Keyword">
then</B>
yOut <= '1'; nS <= s2;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4438">
</A>
<B CLASS="Keyword">
else</B>
yOut <= '0'; nS <= s1;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4440">
</A>
<B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
if</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4442">
</A>
<B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
case</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4444">
</A>
<B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
process</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4446">
</A>
<B CLASS="Keyword">
process</B>
<B CLASS="Keyword">
begin</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4448">
</A>
<B CLASS="Keyword">
wait</B>
<B CLASS="Keyword">
until</B>
clk = '1' ;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4450">
</A>
--Compass Statemachine oneHot pS</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4452">
</A>
pS <= nS;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4454">
</A>
<B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
process</B>
;</P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=4456">
</A>
<B CLASS="Keyword">
end</B>
Mealy;</P>
</DIV>
<HR><P>[ <A HREF="CH12.htm">Chapter start</A> ] [ <A HREF="CH12.6.htm">Previous page</A> ] [ <A HREF="CH12.8.htm">Next page</A> ]</P></BODY>
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