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<TITLE> 12.7 Finite-State Machine Synthesis</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
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<H1 CLASS="Heading1">
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12.7 <A NAME="29506">
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Finite-State Machine Synthesis</H1>
<P CLASS="BodyAfterHead">
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There are three ways to synthesize a <SPAN CLASS="Definition">
finite-state machine</SPAN>
<A NAME="marker=293196">
</A>
(<SPAN CLASS="Definition">
FSM</SPAN>
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</A>
<A NAME="marker=293197">
</A>
):</P>
<OL>
<LI CLASS="NumberFirst">
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Omit any special synthesis directives and let the logic synthesizer operate on the state machine as though it were random logic. This will prevent any reassignment of states or state machine optimization. It is the easiest method and independent of any particular synthesis tool, but is the most inefficient approach in terms of area and performance.</LI>
<LI CLASS="NumberList">
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Use directives to guide the logic synthesis tool to improve or modify state assignment. This approach is dependent on the software that you use.</LI>
<LI CLASS="NumberList">
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Use a special state-machine compiler, separate from the logic synthesizer, to optimize the state machine. You then merge the resulting state machine with the rest of your logic. This method leads to the best results but is harder to use and ties your code to a particular set of software tools, not just the logic synthesizer.</LI>
</OL>
<P CLASS="Body">
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Most synthesis tools require that you write a state machine using a certain style—a special format or template. Synthesis tools may also require that you declare an FSM, the encoding, and the state register using a synthesis directive or special software command. Common FSM encoding options are: </P>
<UL>
<LI CLASS="BulletFirst">
<A NAME="pgfId=293152">
</A>
<A NAME="marker=293151">
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<SPAN CLASS="Definition">
Adjacent encoding</SPAN>
assigns states by the minimum logic difference in the state transition graph. This normally reduces the amount of logic needed to decode each state. The minimum number of bits in the state register for an FSM with <SPAN CLASS="EquationVariables">
n</SPAN>
states is log 2<SPAN CLASS="EquationVariables">
n</SPAN>
. In some tools you may increase the state register width up to <SPAN CLASS="EquationVariables">
n</SPAN>
to generate encoding based on <A NAME="marker=393149">
</A>
Gray codes.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=293154">
</A>
<A NAME="marker=293153">
</A>
<SPAN CLASS="Definition">
One-hot encoding</SPAN>
sets one bit in the state register for each state. This technique seems wasteful. For example, an FSM with 16 states requires 16 flip-flops for one-hot encoding but only four if you use a binary encoding. However, one-hot encoding simplifies the logic and also the interconnect between the logic. One-hot encoding often results in smaller and faster FSMs. This is especially true in programmable ASICs with large amounts of sequential logic relative to combinational logic resources.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=293156">
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<SPAN CLASS="Definition">
Random encoding</SPAN>
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</A>
assigns a random code for each state.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=293157">
</A>
<SPAN CLASS="Definition">
User-specified encoding</SPAN>
<A NAME="marker=393139">
</A>
keeps the explicit state assignment from the HDL.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=293159">
</A>
<SPAN CLASS="Definition">
Moore encoding</SPAN>
<A NAME="marker=293158">
</A>
is useful for FSMs that require fast outputs. A Moore state machine has outputs that depend only on the current state (Mealy state machine outputs depend on the current state and the inputs).</LI>
</UL>
<P CLASS="Body">
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You need to consider how the reset of the state register will be handled in the synthesized hardware. In a programmable ASIC there are often limitations on the polarity of the flip-flop resets. For example, in some FPGAs all flip-flop resets must all be of the same polarity (and this restriction may or may not be present or different for the internal flip-flops and the flip-flops in the I/O cells). Thus, for example, if you try to assign the reset state as <SPAN CLASS="BodyComputer">
'0101'</SPAN>
, it may not be possible to set two flip-flops to <SPAN CLASS="BodyComputer">
'0'</SPAN>
and two flip-flops to <SPAN CLASS="BodyComputer">
'1'</SPAN>
at the same time in an FPGA. This may be handled by assigning the reset state, <SPAN CLASS="BodyComputer">
resSt</SPAN>
, to <SPAN CLASS="BodyComputer">
'0000'</SPAN>
or <SPAN CLASS="BodyComputer">
'1111'</SPAN>
and inverting the appropriate two bits of the state register wherever they are used.</P>
<P CLASS="Body">
<A NAME="pgfId=293178">
</A>
You also need to consider the initial value of the state register in the synthesized hardware. In some reprogrammable FPGAs, after programming is complete the flip-flops may all be initialized to a value that may not correspond to the reset state. Thus if the flip-flops are all set to <SPAN CLASS="BodyComputer">
'1'</SPAN>
at start-up and the reset state is <SPAN CLASS="BodyComputer">
'0000'</SPAN>
, the initial state is <SPAN CLASS="BodyComputer">
'1111'</SPAN>
and not the reset state. For this reason, and also to ensure fail-safe behavior, it is important that the behavior of the FSM is defined for every possible value of the state register.</P>
<DIV>
<H2 CLASS="Heading2">
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12.7.1 FSM Synthesis in Verilog</H2>
<P CLASS="BodyAfterHead">
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The following FSM model uses <A NAME="marker=293046">
</A>
<SPAN CLASS="Definition">
paired processes</SPAN>
. The first process synthesizes to sequential logic and the second process synthesizes to combinational logic: </P>
<P CLASS="ComputerFirstLabelV">
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`define resSt 0</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293049">
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`define S1 1</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293050">
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`define S2 2</P>
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`define S3 3</P>
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<A NAME="pgfId=293052">
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<B CLASS="Keyword">
module</B>
StateMachine_1 (reset, clk, yOutReg);</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293053">
</A>
<B CLASS="Keyword">
input</B>
reset, clk; <B CLASS="Keyword">
output </B>
yOutReg;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293054">
</A>
<B CLASS="Keyword">
reg </B>
yOutReg, yOut; <B CLASS="Keyword">
reg </B>
[1:0] curSt, nextSt;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293055">
</A>
<B CLASS="Keyword">
always</B>
@(<B CLASS="Keyword">
posedge</B>
clk <B CLASS="Keyword">
or</B>
<B CLASS="Keyword">
posedge</B>
reset)</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293056">
</A>
<B CLASS="Keyword">
begin</B>
:Seq //Compass statemachine oneHot curSt</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293057">
</A>
<B CLASS="Keyword">
if</B>
(reset == 1) </P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293058">
</A>
<B CLASS="Keyword">
begin </B>
yOut = 0; yOutReg = yOut; curSt = `resSt; <B CLASS="Keyword">
end</B>
</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293059">
</A>
<B CLASS="Keyword">
else begin</B>
</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293060">
</A>
<B CLASS="Keyword">
case</B>
(curSt)</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293061">
</A>
`resSt:yOut = 0;`S1:yOut = 1;`S2:yOut = 1;`S3:yOut = 1;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293062">
</A>
<B CLASS="Keyword">
default</B>
:yOut = 0;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293063">
</A>
<B CLASS="Keyword">
endcase</B>
</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293064">
</A>
yOutReg = yOut; curSt = nextSt; // ... update the state.</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293065">
</A>
<B CLASS="Keyword">
end</B>
</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293066">
</A>
<B CLASS="Keyword">
end</B>
</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293067">
</A>
<B CLASS="Keyword">
always</B>
@(curSt <B CLASS="Keyword">
or</B>
yOut) // Assign the next state:</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293068">
</A>
<B CLASS="Keyword">
begin</B>
:Comb </P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293069">
</A>
<B CLASS="Keyword">
case</B>
(curSt)</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293070">
</A>
`resSt:nextSt = `S3; `S1:nextSt = `S2;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293071">
</A>
`S2:nextSt = `S1; `S3:nextSt = `S1;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293072">
</A>
<B CLASS="Keyword">
default</B>
:nextSt = `resSt;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293073">
</A>
<B CLASS="Keyword">
endcase</B>
</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293074">
</A>
<B CLASS="Keyword">
end</B>
</P>
<P CLASS="ComputerLastLabelV">
<A NAME="pgfId=293075">
</A>
<B CLASS="Keyword">
endmodule </B>
</P>
<P CLASS="Body">
<A NAME="pgfId=293076">
</A>
Synopsys uses separate <A NAME="marker=395360">
</A>
pseudocomments to define the states and state vector as in the following example:</P>
<P CLASS="ComputerFirstLabelV">
<A NAME="pgfId=293077">
</A>
<B CLASS="Keyword">
module</B>
StateMachine_2 (reset, clk, yOutReg);</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293078">
</A>
<B CLASS="Keyword">
input</B>
reset, clk; <B CLASS="Keyword">
output </B>
yOutReg; <B CLASS="Keyword">
reg </B>
yOutReg, yOut; </P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293080">
</A>
<B CLASS="Keyword">
parameter</B>
<A NAME="24525">
</A>
[1:0] //synopsys enum states </P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293082">
</A>
<A NAME="15758">
</A>
resSt = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293083">
</A>
<B CLASS="Keyword">
reg </B>
[1:0] /* synopsys enum states */ curSt, nextSt;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293084">
</A>
//synopsys state_vector curSt</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293085">
</A>
<B CLASS="Keyword">
always</B>
@(<B CLASS="Keyword">
posedge</B>
clk <B CLASS="Keyword">
or</B>
<B CLASS="Keyword">
posedge</B>
reset) <B CLASS="Keyword">
begin</B>
</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293086">
</A>
<B CLASS="Keyword">
if</B>
(reset == 1) </P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293087">
</A>
<B CLASS="Keyword">
begin </B>
yOut = 0; yOutReg = yOut; curSt = resSt; <B CLASS="Keyword">
end</B>
</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293088">
</A>
<B CLASS="Keyword">
else begin </B>
</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293089">
</A>
<B CLASS="Keyword">
case</B>
(curSt) resSt:yOut = 0;S1:yOut = 1;S2:yOut = 1;S3:yOut = 1; </P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293090">
</A>
<B CLASS="Keyword">
default</B>
:yOut = 0; <B CLASS="Keyword">
endcase</B>
</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293091">
</A>
yOutReg = yOut; curSt = nextSt; <B CLASS="Keyword">
end</B>
</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293092">
</A>
<B CLASS="Keyword">
end </B>
</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293093">
</A>
<B CLASS="Keyword">
always</B>
@(curSt <B CLASS="Keyword">
or</B>
yOut) <B CLASS="Keyword">
begin</B>
</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293094">
</A>
<B CLASS="Keyword">
case</B>
(curSt) </P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293184">
</A>
resSt:nextSt = S3; S1:nextSt = S2; S2:nextSt = S1; S3:nextSt = S1;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293096">
</A>
<B CLASS="Keyword">
default</B>
:nextSt = S1; <B CLASS="Keyword">
endcase</B>
</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293097">
</A>
<B CLASS="Keyword">
end</B>
</P>
<P CLASS="ComputerLastLabelV">
<A NAME="pgfId=293098">
</A>
<B CLASS="Keyword">
endmodule </B>
</P>
<P CLASS="Body">
<A NAME="pgfId=293105">
</A>
To change encoding we can assign states explicitly by altering lines <A HREF="#24525" CLASS="XRef">
3</A>
–<A HREF="#15758" CLASS="XRef">
4</A>
to the following, for example:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=293106">
</A>
<B CLASS="Keyword">
parameter</B>
[3:0] //synopsys enum states </P>
<P CLASS="ComputerLast">
<A NAME="pgfId=293107">
</A>
resSt = 4'b0000, S1 = 4'b0010, S2 = 4'b0100, S3 = 4'b1000;</P>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=293015">
</A>
12.7.2 FSM Synthesis in VHDL</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=4350">
</A>
The first architecture that follows is a template for a <A NAME="marker=288025">
</A>
Moore state machine:</P>
<P CLASS="ComputerFirstLabel">
<A NAME="pgfId=288044">
</A>
<B CLASS="Keyword">
library</B>
IEEE; <B CLASS="Keyword">
use</B>
IEEE.STD_LOGIC_1164.<B CLASS="Keyword">
all</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4352">
</A>
<B CLASS="Keyword">
entity</B>
SM1 <B CLASS="Keyword">
is</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4354">
</A>
<B CLASS="Keyword">
port</B>
(aIn, clk : <B CLASS="Keyword">
in</B>
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